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@@ -667,6 +667,7 @@ static const u32 ar9485_1_0_pcie_phy_clkreq_enable_L1[][2] = {
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static const u32 ar9485_1_0_soc_preamble[][2] = {
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static const u32 ar9485_1_0_soc_preamble[][2] = {
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/* Addr allmodes */
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/* Addr allmodes */
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+ {0x00004090, 0x00aa10aa},
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{0x000040a4, 0x00a0c9c9},
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{0x000040a4, 0x00a0c9c9},
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{0x00007048, 0x00000004},
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{0x00007048, 0x00000004},
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};
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};
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@@ -1708,6 +1709,7 @@ static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
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static const u32 ar9485_1_1_soc_preamble[][2] = {
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static const u32 ar9485_1_1_soc_preamble[][2] = {
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/* Addr allmodes */
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/* Addr allmodes */
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{0x00004014, 0xba280400},
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{0x00004014, 0xba280400},
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+ {0x00004090, 0x00aa10aa},
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{0x000040a4, 0x00a0c9c9},
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{0x000040a4, 0x00a0c9c9},
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{0x00007010, 0x00000022},
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{0x00007010, 0x00000022},
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{0x00007020, 0x00000000},
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{0x00007020, 0x00000000},
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