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@@ -80,7 +80,6 @@
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#define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */
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#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */
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#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
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-#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */
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#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
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#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
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#define X86_FEATURE_SYSCALL32 (3*32+14) /* "" syscall in ia32 userspace */
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@@ -92,6 +91,8 @@
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#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */
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#define X86_FEATURE_AMDC1E (3*32+21) /* AMD C1E detected */
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#define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */
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+#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
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+#define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */
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/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
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#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */
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@@ -117,6 +118,7 @@
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#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
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#define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */
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#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
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+#define X86_FEATURE_HYPERVISOR (4*32+31) /* Running on a hypervisor */
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/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
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#define X86_FEATURE_XSTORE (5*32+ 2) /* "rng" RNG present (xstore) */
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@@ -237,6 +239,7 @@ extern const char * const x86_power_flags[32];
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#define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2)
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#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC)
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#define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE)
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+#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR)
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#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
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# define cpu_has_invlpg 1
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Ingo Molnar