|
@@ -291,11 +291,6 @@ struct ni_65xx_private {
|
|
|
unsigned short dio_direction[NI_65XX_MAX_NUM_PORTS];
|
|
|
};
|
|
|
|
|
|
-static inline struct ni_65xx_private *private(struct comedi_device *dev)
|
|
|
-{
|
|
|
- return dev->private;
|
|
|
-}
|
|
|
-
|
|
|
struct ni_65xx_subdevice_private {
|
|
|
unsigned base_port;
|
|
|
};
|
|
@@ -319,6 +314,7 @@ static int ni_65xx_config_filter(struct comedi_device *dev,
|
|
|
struct comedi_subdevice *s,
|
|
|
struct comedi_insn *insn, unsigned int *data)
|
|
|
{
|
|
|
+ struct ni_65xx_private *devpriv = dev->private;
|
|
|
const unsigned chan = CR_CHAN(insn->chanspec);
|
|
|
const unsigned port =
|
|
|
sprivate(s)->base_port + ni_65xx_port_by_channel(chan);
|
|
@@ -335,22 +331,22 @@ static int ni_65xx_config_filter(struct comedi_device *dev,
|
|
|
interval = max_filter_interval;
|
|
|
data[1] = interval * filter_resolution_ns;
|
|
|
|
|
|
- if (interval != private(dev)->filter_interval) {
|
|
|
+ if (interval != devpriv->filter_interval) {
|
|
|
writeb(interval,
|
|
|
- private(dev)->mite->daq_io_addr +
|
|
|
+ devpriv->mite->daq_io_addr +
|
|
|
Filter_Interval);
|
|
|
- private(dev)->filter_interval = interval;
|
|
|
+ devpriv->filter_interval = interval;
|
|
|
}
|
|
|
|
|
|
- private(dev)->filter_enable[port] |=
|
|
|
+ devpriv->filter_enable[port] |=
|
|
|
1 << (chan % ni_65xx_channels_per_port);
|
|
|
} else {
|
|
|
- private(dev)->filter_enable[port] &=
|
|
|
+ devpriv->filter_enable[port] &=
|
|
|
~(1 << (chan % ni_65xx_channels_per_port));
|
|
|
}
|
|
|
|
|
|
- writeb(private(dev)->filter_enable[port],
|
|
|
- private(dev)->mite->daq_io_addr + Filter_Enable(port));
|
|
|
+ writeb(devpriv->filter_enable[port],
|
|
|
+ devpriv->mite->daq_io_addr + Filter_Enable(port));
|
|
|
|
|
|
return 2;
|
|
|
}
|
|
@@ -359,6 +355,7 @@ static int ni_65xx_dio_insn_config(struct comedi_device *dev,
|
|
|
struct comedi_subdevice *s,
|
|
|
struct comedi_insn *insn, unsigned int *data)
|
|
|
{
|
|
|
+ struct ni_65xx_private *devpriv = dev->private;
|
|
|
unsigned port;
|
|
|
|
|
|
if (insn->n < 1)
|
|
@@ -372,21 +369,21 @@ static int ni_65xx_dio_insn_config(struct comedi_device *dev,
|
|
|
case INSN_CONFIG_DIO_OUTPUT:
|
|
|
if (s->type != COMEDI_SUBD_DIO)
|
|
|
return -EINVAL;
|
|
|
- private(dev)->dio_direction[port] = COMEDI_OUTPUT;
|
|
|
- writeb(0, private(dev)->mite->daq_io_addr + Port_Select(port));
|
|
|
+ devpriv->dio_direction[port] = COMEDI_OUTPUT;
|
|
|
+ writeb(0, devpriv->mite->daq_io_addr + Port_Select(port));
|
|
|
return 1;
|
|
|
break;
|
|
|
case INSN_CONFIG_DIO_INPUT:
|
|
|
if (s->type != COMEDI_SUBD_DIO)
|
|
|
return -EINVAL;
|
|
|
- private(dev)->dio_direction[port] = COMEDI_INPUT;
|
|
|
- writeb(1, private(dev)->mite->daq_io_addr + Port_Select(port));
|
|
|
+ devpriv->dio_direction[port] = COMEDI_INPUT;
|
|
|
+ writeb(1, devpriv->mite->daq_io_addr + Port_Select(port));
|
|
|
return 1;
|
|
|
break;
|
|
|
case INSN_CONFIG_DIO_QUERY:
|
|
|
if (s->type != COMEDI_SUBD_DIO)
|
|
|
return -EINVAL;
|
|
|
- data[1] = private(dev)->dio_direction[port];
|
|
|
+ data[1] = devpriv->dio_direction[port];
|
|
|
return insn->n;
|
|
|
break;
|
|
|
default:
|
|
@@ -399,6 +396,7 @@ static int ni_65xx_dio_insn_bits(struct comedi_device *dev,
|
|
|
struct comedi_subdevice *s,
|
|
|
struct comedi_insn *insn, unsigned int *data)
|
|
|
{
|
|
|
+ struct ni_65xx_private *devpriv = dev->private;
|
|
|
unsigned base_bitfield_channel;
|
|
|
const unsigned max_ports_per_bitfield = 5;
|
|
|
unsigned read_bits = 0;
|
|
@@ -432,18 +430,18 @@ static int ni_65xx_dio_insn_bits(struct comedi_device *dev,
|
|
|
port_data &= 0xff;
|
|
|
if (port_mask) {
|
|
|
unsigned bits;
|
|
|
- private(dev)->output_bits[port] &= ~port_mask;
|
|
|
- private(dev)->output_bits[port] |=
|
|
|
+ devpriv->output_bits[port] &= ~port_mask;
|
|
|
+ devpriv->output_bits[port] |=
|
|
|
port_data & port_mask;
|
|
|
- bits = private(dev)->output_bits[port];
|
|
|
+ bits = devpriv->output_bits[port];
|
|
|
if (board(dev)->invert_outputs)
|
|
|
bits = ~bits;
|
|
|
writeb(bits,
|
|
|
- private(dev)->mite->daq_io_addr +
|
|
|
+ devpriv->mite->daq_io_addr +
|
|
|
Port_Data(port));
|
|
|
}
|
|
|
port_read_bits =
|
|
|
- readb(private(dev)->mite->daq_io_addr + Port_Data(port));
|
|
|
+ readb(devpriv->mite->daq_io_addr + Port_Data(port));
|
|
|
if (s->type == COMEDI_SUBD_DO && board(dev)->invert_outputs) {
|
|
|
/* Outputs inverted, so invert value read back from
|
|
|
* DO subdevice. (Does not apply to boards with DIO
|
|
@@ -464,17 +462,18 @@ static int ni_65xx_dio_insn_bits(struct comedi_device *dev,
|
|
|
static irqreturn_t ni_65xx_interrupt(int irq, void *d)
|
|
|
{
|
|
|
struct comedi_device *dev = d;
|
|
|
+ struct ni_65xx_private *devpriv = dev->private;
|
|
|
struct comedi_subdevice *s = &dev->subdevices[2];
|
|
|
unsigned int status;
|
|
|
|
|
|
- status = readb(private(dev)->mite->daq_io_addr + Change_Status);
|
|
|
+ status = readb(devpriv->mite->daq_io_addr + Change_Status);
|
|
|
if ((status & MasterInterruptStatus) == 0)
|
|
|
return IRQ_NONE;
|
|
|
if ((status & EdgeStatus) == 0)
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
writeb(ClrEdge | ClrOverflow,
|
|
|
- private(dev)->mite->daq_io_addr + Clear_Register);
|
|
|
+ devpriv->mite->daq_io_addr + Clear_Register);
|
|
|
|
|
|
comedi_buf_put(s->async, 0);
|
|
|
s->async->events |= COMEDI_CB_EOS;
|
|
@@ -543,13 +542,14 @@ static int ni_65xx_intr_cmdtest(struct comedi_device *dev,
|
|
|
static int ni_65xx_intr_cmd(struct comedi_device *dev,
|
|
|
struct comedi_subdevice *s)
|
|
|
{
|
|
|
+ struct ni_65xx_private *devpriv = dev->private;
|
|
|
/* struct comedi_cmd *cmd = &s->async->cmd; */
|
|
|
|
|
|
writeb(ClrEdge | ClrOverflow,
|
|
|
- private(dev)->mite->daq_io_addr + Clear_Register);
|
|
|
+ devpriv->mite->daq_io_addr + Clear_Register);
|
|
|
writeb(FallingEdgeIntEnable | RisingEdgeIntEnable |
|
|
|
MasterInterruptEnable | EdgeIntEnable,
|
|
|
- private(dev)->mite->daq_io_addr + Master_Interrupt_Control);
|
|
|
+ devpriv->mite->daq_io_addr + Master_Interrupt_Control);
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
@@ -557,8 +557,9 @@ static int ni_65xx_intr_cmd(struct comedi_device *dev,
|
|
|
static int ni_65xx_intr_cancel(struct comedi_device *dev,
|
|
|
struct comedi_subdevice *s)
|
|
|
{
|
|
|
- writeb(0x00,
|
|
|
- private(dev)->mite->daq_io_addr + Master_Interrupt_Control);
|
|
|
+ struct ni_65xx_private *devpriv = dev->private;
|
|
|
+
|
|
|
+ writeb(0x00, devpriv->mite->daq_io_addr + Master_Interrupt_Control);
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
@@ -576,35 +577,37 @@ static int ni_65xx_intr_insn_config(struct comedi_device *dev,
|
|
|
struct comedi_insn *insn,
|
|
|
unsigned int *data)
|
|
|
{
|
|
|
+ struct ni_65xx_private *devpriv = dev->private;
|
|
|
+
|
|
|
if (insn->n < 1)
|
|
|
return -EINVAL;
|
|
|
if (data[0] != INSN_CONFIG_CHANGE_NOTIFY)
|
|
|
return -EINVAL;
|
|
|
|
|
|
writeb(data[1],
|
|
|
- private(dev)->mite->daq_io_addr +
|
|
|
+ devpriv->mite->daq_io_addr +
|
|
|
Rising_Edge_Detection_Enable(0));
|
|
|
writeb(data[1] >> 8,
|
|
|
- private(dev)->mite->daq_io_addr +
|
|
|
+ devpriv->mite->daq_io_addr +
|
|
|
Rising_Edge_Detection_Enable(0x10));
|
|
|
writeb(data[1] >> 16,
|
|
|
- private(dev)->mite->daq_io_addr +
|
|
|
+ devpriv->mite->daq_io_addr +
|
|
|
Rising_Edge_Detection_Enable(0x20));
|
|
|
writeb(data[1] >> 24,
|
|
|
- private(dev)->mite->daq_io_addr +
|
|
|
+ devpriv->mite->daq_io_addr +
|
|
|
Rising_Edge_Detection_Enable(0x30));
|
|
|
|
|
|
writeb(data[2],
|
|
|
- private(dev)->mite->daq_io_addr +
|
|
|
+ devpriv->mite->daq_io_addr +
|
|
|
Falling_Edge_Detection_Enable(0));
|
|
|
writeb(data[2] >> 8,
|
|
|
- private(dev)->mite->daq_io_addr +
|
|
|
+ devpriv->mite->daq_io_addr +
|
|
|
Falling_Edge_Detection_Enable(0x10));
|
|
|
writeb(data[2] >> 16,
|
|
|
- private(dev)->mite->daq_io_addr +
|
|
|
+ devpriv->mite->daq_io_addr +
|
|
|
Falling_Edge_Detection_Enable(0x20));
|
|
|
writeb(data[2] >> 24,
|
|
|
- private(dev)->mite->daq_io_addr +
|
|
|
+ devpriv->mite->daq_io_addr +
|
|
|
Falling_Edge_Detection_Enable(0x30));
|
|
|
|
|
|
return 2;
|
|
@@ -627,32 +630,34 @@ ni_65xx_find_boardinfo(struct pci_dev *pcidev)
|
|
|
static int __devinit ni_65xx_attach_pci(struct comedi_device *dev,
|
|
|
struct pci_dev *pcidev)
|
|
|
{
|
|
|
+ struct ni_65xx_private *devpriv;
|
|
|
struct comedi_subdevice *s;
|
|
|
unsigned i;
|
|
|
int ret;
|
|
|
|
|
|
- ret = alloc_private(dev, sizeof(struct ni_65xx_private));
|
|
|
- if (ret < 0)
|
|
|
+ ret = alloc_private(dev, sizeof(*devpriv));
|
|
|
+ if (ret)
|
|
|
return ret;
|
|
|
+ devpriv = dev->private;
|
|
|
|
|
|
dev->board_ptr = ni_65xx_find_boardinfo(pcidev);
|
|
|
if (!dev->board_ptr)
|
|
|
return -ENODEV;
|
|
|
|
|
|
- private(dev)->mite = mite_alloc(pcidev);
|
|
|
- if (!private(dev)->mite)
|
|
|
+ devpriv->mite = mite_alloc(pcidev);
|
|
|
+ if (!devpriv->mite)
|
|
|
return -ENOMEM;
|
|
|
|
|
|
- ret = mite_setup(private(dev)->mite);
|
|
|
+ ret = mite_setup(devpriv->mite);
|
|
|
if (ret < 0) {
|
|
|
dev_warn(dev->class_dev, "error setting up mite\n");
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
dev->board_name = board(dev)->name;
|
|
|
- dev->irq = mite_irq(private(dev)->mite);
|
|
|
+ dev->irq = mite_irq(devpriv->mite);
|
|
|
dev_info(dev->class_dev, "board: %s, ID=0x%02x", dev->board_name,
|
|
|
- readb(private(dev)->mite->daq_io_addr + ID_Register));
|
|
|
+ readb(devpriv->mite->daq_io_addr + ID_Register));
|
|
|
|
|
|
ret = comedi_alloc_subdevices(dev, 4);
|
|
|
if (ret)
|
|
@@ -710,7 +715,7 @@ static int __devinit ni_65xx_attach_pci(struct comedi_device *dev,
|
|
|
for (i = 0; i < board(dev)->num_dio_ports; ++i) {
|
|
|
/* configure all ports for input */
|
|
|
writeb(0x1,
|
|
|
- private(dev)->mite->daq_io_addr +
|
|
|
+ devpriv->mite->daq_io_addr +
|
|
|
Port_Select(i));
|
|
|
}
|
|
|
} else {
|
|
@@ -732,21 +737,21 @@ static int __devinit ni_65xx_attach_pci(struct comedi_device *dev,
|
|
|
|
|
|
for (i = 0; i < ni_65xx_total_num_ports(board(dev)); ++i) {
|
|
|
writeb(0x00,
|
|
|
- private(dev)->mite->daq_io_addr + Filter_Enable(i));
|
|
|
+ devpriv->mite->daq_io_addr + Filter_Enable(i));
|
|
|
if (board(dev)->invert_outputs)
|
|
|
writeb(0x01,
|
|
|
- private(dev)->mite->daq_io_addr + Port_Data(i));
|
|
|
+ devpriv->mite->daq_io_addr + Port_Data(i));
|
|
|
else
|
|
|
writeb(0x00,
|
|
|
- private(dev)->mite->daq_io_addr + Port_Data(i));
|
|
|
+ devpriv->mite->daq_io_addr + Port_Data(i));
|
|
|
}
|
|
|
writeb(ClrEdge | ClrOverflow,
|
|
|
- private(dev)->mite->daq_io_addr + Clear_Register);
|
|
|
+ devpriv->mite->daq_io_addr + Clear_Register);
|
|
|
writeb(0x00,
|
|
|
- private(dev)->mite->daq_io_addr + Master_Interrupt_Control);
|
|
|
+ devpriv->mite->daq_io_addr + Master_Interrupt_Control);
|
|
|
|
|
|
/* Set filter interval to 0 (32bit reg) */
|
|
|
- writeb(0x00000000, private(dev)->mite->daq_io_addr + Filter_Interval);
|
|
|
+ writeb(0x00000000, devpriv->mite->daq_io_addr + Filter_Interval);
|
|
|
|
|
|
ret = request_irq(dev->irq, ni_65xx_interrupt, IRQF_SHARED,
|
|
|
"ni_65xx", dev);
|
|
@@ -760,15 +765,16 @@ static int __devinit ni_65xx_attach_pci(struct comedi_device *dev,
|
|
|
|
|
|
static void ni_65xx_detach(struct comedi_device *dev)
|
|
|
{
|
|
|
- if (private(dev) && private(dev)->mite
|
|
|
- && private(dev)->mite->daq_io_addr) {
|
|
|
+ struct ni_65xx_private *devpriv = dev->private;
|
|
|
+
|
|
|
+ if (devpriv && devpriv->mite && devpriv->mite->daq_io_addr) {
|
|
|
writeb(0x00,
|
|
|
- private(dev)->mite->daq_io_addr +
|
|
|
+ devpriv->mite->daq_io_addr +
|
|
|
Master_Interrupt_Control);
|
|
|
}
|
|
|
if (dev->irq)
|
|
|
free_irq(dev->irq, dev);
|
|
|
- if (private(dev)) {
|
|
|
+ if (devpriv) {
|
|
|
struct comedi_subdevice *s;
|
|
|
unsigned i;
|
|
|
|
|
@@ -777,9 +783,9 @@ static void ni_65xx_detach(struct comedi_device *dev)
|
|
|
kfree(s->private);
|
|
|
s->private = NULL;
|
|
|
}
|
|
|
- if (private(dev)->mite) {
|
|
|
- mite_unsetup(private(dev)->mite);
|
|
|
- mite_free(private(dev)->mite);
|
|
|
+ if (devpriv->mite) {
|
|
|
+ mite_unsetup(devpriv->mite);
|
|
|
+ mite_free(devpriv->mite);
|
|
|
}
|
|
|
}
|
|
|
}
|