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@@ -6959,7 +6959,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
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{
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u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
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u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
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- u32 pcu_mbox;
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+ u32 pcu_mbox, rc6_mask = 0;
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int cur_freq, min_freq, max_freq;
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int i;
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@@ -6990,9 +6990,12 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
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I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
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I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
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+ if (i915_enable_rc6)
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+ rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
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+ GEN6_RC_CTL_RC6_ENABLE;
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+
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I915_WRITE(GEN6_RC_CONTROL,
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- GEN6_RC_CTL_RC6p_ENABLE |
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- GEN6_RC_CTL_RC6_ENABLE |
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+ rc6_mask |
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GEN6_RC_CTL_EI_MODE(1) |
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GEN6_RC_CTL_HW_ENABLE);
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