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@@ -910,7 +910,7 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_mode_info *mode_info = &rdev->mode_info;
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int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
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- uint16_t data_offset;
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+ uint16_t data_offset, misc;
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union lvds_info *lvds_info;
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uint8_t frev, crev;
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struct radeon_encoder_atom_dig *lvds = NULL;
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@@ -949,6 +949,19 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
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lvds->panel_pwr_delay =
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le16_to_cpu(lvds_info->info.usOffDelayInMs);
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lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
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+
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+ misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
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+ if (misc & ATOM_VSYNC_POLARITY)
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+ lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
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+ if (misc & ATOM_HSYNC_POLARITY)
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+ lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
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+ if (misc & ATOM_COMPOSITESYNC)
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+ lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
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+ if (misc & ATOM_INTERLACE)
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+ lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
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+ if (misc & ATOM_DOUBLE_CLOCK_MODE)
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+ lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
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+
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/* set crtc values */
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drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
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