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@@ -105,6 +105,7 @@ static const struct ipr_chip_cfg_t ipr_chip_cfg[] = {
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{ /* Gemstone, Citrine, Obsidian, and Obsidian-E */
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{ /* Gemstone, Citrine, Obsidian, and Obsidian-E */
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.mailbox = 0x0042C,
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.mailbox = 0x0042C,
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.cache_line_size = 0x20,
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.cache_line_size = 0x20,
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+ .clear_isr = 1,
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{
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{
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.set_interrupt_mask_reg = 0x0022C,
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.set_interrupt_mask_reg = 0x0022C,
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.clr_interrupt_mask_reg = 0x00230,
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.clr_interrupt_mask_reg = 0x00230,
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@@ -127,6 +128,7 @@ static const struct ipr_chip_cfg_t ipr_chip_cfg[] = {
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{ /* Snipe and Scamp */
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{ /* Snipe and Scamp */
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.mailbox = 0x0052C,
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.mailbox = 0x0052C,
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.cache_line_size = 0x20,
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.cache_line_size = 0x20,
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+ .clear_isr = 1,
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{
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{
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.set_interrupt_mask_reg = 0x00288,
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.set_interrupt_mask_reg = 0x00288,
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.clr_interrupt_mask_reg = 0x0028C,
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.clr_interrupt_mask_reg = 0x0028C,
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@@ -149,6 +151,7 @@ static const struct ipr_chip_cfg_t ipr_chip_cfg[] = {
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{ /* CRoC */
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{ /* CRoC */
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.mailbox = 0x00044,
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.mailbox = 0x00044,
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.cache_line_size = 0x20,
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.cache_line_size = 0x20,
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+ .clear_isr = 0,
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{
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{
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.set_interrupt_mask_reg = 0x00010,
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.set_interrupt_mask_reg = 0x00010,
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.clr_interrupt_mask_reg = 0x00018,
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.clr_interrupt_mask_reg = 0x00018,
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@@ -5049,12 +5052,14 @@ static irqreturn_t ipr_handle_other_interrupt(struct ipr_ioa_cfg *ioa_cfg,
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del_timer(&ioa_cfg->reset_cmd->timer);
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del_timer(&ioa_cfg->reset_cmd->timer);
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ipr_reset_ioa_job(ioa_cfg->reset_cmd);
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ipr_reset_ioa_job(ioa_cfg->reset_cmd);
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} else if ((int_reg & IPR_PCII_HRRQ_UPDATED) == int_reg) {
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} else if ((int_reg & IPR_PCII_HRRQ_UPDATED) == int_reg) {
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- if (ipr_debug && printk_ratelimit())
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- dev_err(&ioa_cfg->pdev->dev,
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- "Spurious interrupt detected. 0x%08X\n", int_reg);
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- writel(IPR_PCII_HRRQ_UPDATED, ioa_cfg->regs.clr_interrupt_reg32);
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- int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
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- return IRQ_NONE;
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+ if (ioa_cfg->clear_isr) {
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+ if (ipr_debug && printk_ratelimit())
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+ dev_err(&ioa_cfg->pdev->dev,
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+ "Spurious interrupt detected. 0x%08X\n", int_reg);
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+ writel(IPR_PCII_HRRQ_UPDATED, ioa_cfg->regs.clr_interrupt_reg32);
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+ int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
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+ return IRQ_NONE;
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+ }
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} else {
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} else {
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if (int_reg & IPR_PCII_IOA_UNIT_CHECKED)
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if (int_reg & IPR_PCII_IOA_UNIT_CHECKED)
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ioa_cfg->ioa_unit_checked = 1;
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ioa_cfg->ioa_unit_checked = 1;
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@@ -5154,6 +5159,9 @@ static irqreturn_t ipr_isr(int irq, void *devp)
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}
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}
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}
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}
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+ if (ipr_cmd && !ioa_cfg->clear_isr)
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+ break;
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+
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if (ipr_cmd != NULL) {
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if (ipr_cmd != NULL) {
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/* Clear the PCI interrupt */
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/* Clear the PCI interrupt */
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num_hrrq = 0;
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num_hrrq = 0;
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@@ -8769,6 +8777,7 @@ static int __devinit ipr_probe_ioa(struct pci_dev *pdev,
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/* set SIS 32 or SIS 64 */
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/* set SIS 32 or SIS 64 */
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ioa_cfg->sis64 = ioa_cfg->ipr_chip->sis_type == IPR_SIS64 ? 1 : 0;
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ioa_cfg->sis64 = ioa_cfg->ipr_chip->sis_type == IPR_SIS64 ? 1 : 0;
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ioa_cfg->chip_cfg = ioa_cfg->ipr_chip->cfg;
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ioa_cfg->chip_cfg = ioa_cfg->ipr_chip->cfg;
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+ ioa_cfg->clear_isr = ioa_cfg->chip_cfg->clear_isr;
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if (ipr_transop_timeout)
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if (ipr_transop_timeout)
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ioa_cfg->transop_timeout = ipr_transop_timeout;
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ioa_cfg->transop_timeout = ipr_transop_timeout;
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