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@@ -86,6 +86,13 @@ enum {
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/* HOST_SLOT_STAT bits */
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HOST_SSTAT_ATTN = (1 << 31),
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+ /* HOST_CTRL bits */
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+ HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
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+ HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
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+ HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
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+ HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
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+ HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
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+
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/*
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* Port registers
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* (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
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@@ -142,7 +149,11 @@ enum {
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PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
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PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
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PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
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- PORT_IRQ_UNK_FIS = (1 << 6), /* Unknown FIS received */
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+ PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
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+ PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
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+ PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
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+ PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
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+ PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
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PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
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/* bits[27:16] are unmasked (raw) */
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