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@@ -94,7 +94,7 @@
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#include <linux/dmi.h>
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#define DRV_NAME "ata_piix"
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-#define DRV_VERSION "2.11"
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+#define DRV_VERSION "2.12"
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enum {
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PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
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@@ -130,6 +130,7 @@ enum {
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ich6m_sata_ahci = 8,
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ich8_sata_ahci = 9,
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piix_pata_mwdma = 10, /* PIIX3 MWDMA only */
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+ tolapai_sata_ahci = 11,
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/* constants for mapping table */
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P0 = 0, /* port 0 */
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@@ -253,6 +254,8 @@ static const struct pci_device_id piix_pci_tbl[] = {
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{ 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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/* SATA Controller IDE (ICH9M) */
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{ 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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+ /* SATA Controller IDE (Tolapai) */
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+ { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
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{ } /* terminate list */
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};
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@@ -441,12 +444,25 @@ static const struct piix_map_db ich8_map_db = {
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},
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};
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+static const struct piix_map_db tolapai_map_db = {
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+ .mask = 0x3,
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+ .port_enable = 0x3,
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+ .map = {
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+ /* PM PS SM SS MAP */
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+ { P0, NA, P1, NA }, /* 00b */
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+ { RV, RV, RV, RV }, /* 01b */
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+ { RV, RV, RV, RV }, /* 10b */
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+ { RV, RV, RV, RV },
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+ },
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+};
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+
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static const struct piix_map_db *piix_map_db_table[] = {
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[ich5_sata] = &ich5_map_db,
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[ich6_sata] = &ich6_map_db,
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[ich6_sata_ahci] = &ich6_map_db,
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[ich6m_sata_ahci] = &ich6m_map_db,
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[ich8_sata_ahci] = &ich8_map_db,
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+ [tolapai_sata_ahci] = &tolapai_map_db,
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};
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static struct ata_port_info piix_port_info[] = {
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@@ -560,6 +576,17 @@ static struct ata_port_info piix_port_info[] = {
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.mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
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.port_ops = &piix_pata_ops,
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},
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+
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+ /* tolapai_sata_ahci: 11: */
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+ {
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+ .sht = &piix_sht,
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+ .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
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+ PIIX_FLAG_AHCI,
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+ .pio_mask = 0x1f, /* pio0-4 */
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+ .mwdma_mask = 0x07, /* mwdma0-2 */
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+ .udma_mask = ATA_UDMA6,
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+ .port_ops = &piix_sata_ops,
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+ },
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};
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static struct pci_bits piix_enable_bits[] = {
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@@ -907,6 +934,13 @@ static int piix_broken_suspend(void)
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DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
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},
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},
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+ {
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+ .ident = "Satellite U200",
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+ .matches = {
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+ DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
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+ DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
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+ },
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+ },
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{
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.ident = "Satellite U205",
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.matches = {
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@@ -1139,6 +1173,39 @@ static void __devinit piix_init_sata_map(struct pci_dev *pdev,
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hpriv->map = map;
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}
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+static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
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+{
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+ static struct dmi_system_id sysids[] = {
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+ {
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+ /* Clevo M570U sets IOCFG bit 18 if the cdrom
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+ * isn't used to boot the system which
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+ * disables the channel.
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+ */
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+ .ident = "M570U",
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+ .matches = {
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+ DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
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+ DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
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+ },
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+ },
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+ };
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+ u32 iocfg;
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+
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+ if (!dmi_check_system(sysids))
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+ return;
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+
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+ /* The datasheet says that bit 18 is NOOP but certain systems
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+ * seem to use it to disable a channel. Clear the bit on the
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+ * affected systems.
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+ */
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+ pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
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+ if (iocfg & (1 << 18)) {
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+ dev_printk(KERN_INFO, &pdev->dev,
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+ "applying IOCFG bit18 quirk\n");
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+ iocfg &= ~(1 << 18);
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+ pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
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+ }
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+}
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+
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/**
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* piix_init_one - Register PIIX ATA PCI device with kernel services
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* @pdev: PCI device to register
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@@ -1200,6 +1267,9 @@ static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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piix_map_db_table[ent->driver_data]);
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}
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+ /* apply IOCFG bit18 quirk */
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+ piix_iocfg_bit18_quirk(pdev);
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+
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/* On ICH5, some BIOSen disable the interrupt using the
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* PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
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* On ICH6, this bit has the same effect, but only when
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