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@@ -77,11 +77,11 @@ static inline void fill_cip_header(struct CIP_header *cip,
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See the Texas Instruments OHCI 1394 chipset documentation.
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*/
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-struct output_more_immediate { u32 q[8]; };
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-struct output_more { u32 q[4]; };
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-struct output_last { u32 q[4]; };
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-struct input_more { u32 q[4]; };
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-struct input_last { u32 q[4]; };
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+struct output_more_immediate { __le32 q[8]; };
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+struct output_more { __le32 q[4]; };
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+struct output_last { __le32 q[4]; };
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+struct input_more { __le32 q[4]; };
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+struct input_last { __le32 q[4]; };
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/* outputs */
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@@ -92,9 +92,9 @@ static inline void fill_output_more_immediate(struct output_more_immediate *omi,
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unsigned int payload_size)
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{
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omi->q[0] = cpu_to_le32(0x02000000 | 8); /* OUTPUT_MORE_IMMEDIATE; 8 is the size of the IT header */
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- omi->q[1] = 0;
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- omi->q[2] = 0;
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- omi->q[3] = 0;
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+ omi->q[1] = cpu_to_le32(0);
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+ omi->q[2] = cpu_to_le32(0);
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+ omi->q[3] = cpu_to_le32(0);
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/* IT packet header */
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omi->q[4] = cpu_to_le32( (0x0 << 16) /* IEEE1394_SPEED_100 */
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@@ -106,8 +106,8 @@ static inline void fill_output_more_immediate(struct output_more_immediate *omi,
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/* reserved field; mimic behavior of my Sony DSR-40 */
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omi->q[5] = cpu_to_le32((payload_size << 16) | (0x7F << 8) | 0xA0);
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- omi->q[6] = 0;
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- omi->q[7] = 0;
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+ omi->q[6] = cpu_to_le32(0);
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+ omi->q[7] = cpu_to_le32(0);
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}
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static inline void fill_output_more(struct output_more *om,
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@@ -116,8 +116,8 @@ static inline void fill_output_more(struct output_more *om,
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{
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om->q[0] = cpu_to_le32(data_size);
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om->q[1] = cpu_to_le32(data_phys_addr);
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- om->q[2] = 0;
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- om->q[3] = 0;
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+ om->q[2] = cpu_to_le32(0);
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+ om->q[3] = cpu_to_le32(0);
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}
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static inline void fill_output_last(struct output_last *ol,
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@@ -140,8 +140,8 @@ static inline void fill_output_last(struct output_last *ol,
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ol->q[0] = cpu_to_le32(temp);
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ol->q[1] = cpu_to_le32(data_phys_addr);
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- ol->q[2] = 0;
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- ol->q[3] = 0;
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+ ol->q[2] = cpu_to_le32(0);
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+ ol->q[3] = cpu_to_le32(0);
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}
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/* inputs */
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@@ -161,8 +161,8 @@ static inline void fill_input_more(struct input_more *im,
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im->q[0] = cpu_to_le32(temp);
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im->q[1] = cpu_to_le32(data_phys_addr);
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- im->q[2] = 0; /* branchAddress and Z not use in packet-per-buffer mode */
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- im->q[3] = 0; /* xferStatus & resCount, resCount must be initialize to data_size */
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+ im->q[2] = cpu_to_le32(0); /* branchAddress and Z not use in packet-per-buffer mode */
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+ im->q[3] = cpu_to_le32(0); /* xferStatus & resCount, resCount must be initialize to data_size */
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}
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static inline void fill_input_last(struct input_last *il,
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@@ -331,7 +331,7 @@ struct frame {
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/* points to status/timestamp field of first DMA packet */
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/* (we'll check it later to monitor timestamp accuracy) */
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- u32 *frame_begin_timestamp;
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+ __le32 *frame_begin_timestamp;
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/* the timestamp we assigned to the first packet in the frame */
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u32 assigned_timestamp;
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@@ -348,15 +348,15 @@ struct frame {
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that can cause interrupts. We'll check these from the
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interrupt handler.
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*/
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- u32 *mid_frame_timestamp;
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- u32 *frame_end_timestamp;
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+ __le32 *mid_frame_timestamp;
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+ __le32 *frame_end_timestamp;
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/* branch address field of final packet. This is effectively
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the "tail" in the chain of DMA descriptor blocks.
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We will fill it with the address of the first DMA descriptor
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block in the subsequent frame, once it is ready.
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*/
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- u32 *frame_end_branch;
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+ __le32 *frame_end_branch;
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/* the number of descriptors in the first descriptor block
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of the frame. Needed to start DMA */
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@@ -365,10 +365,10 @@ struct frame {
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struct packet {
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- u16 timestamp;
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+ __le16 timestamp;
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u16 invalid;
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u16 iso_header;
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- u16 data_length;
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+ __le16 data_length;
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u32 cip_h1;
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u32 cip_h2;
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unsigned char data[480];
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