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@@ -770,9 +770,14 @@ static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)
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return 1;
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}
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- /* it might be unflagged overflow */
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- rdmsrl(hwc->event_base + hwc->idx, v);
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- if (!(v & ARCH_P4_CNTRVAL_MASK))
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+ /*
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+ * In some circumstances the overflow might issue an NMI but did
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+ * not set P4_CCCR_OVF bit. Because a counter holds a negative value
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+ * we simply check for high bit being set, if it's cleared it means
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+ * the counter has reached zero value and continued counting before
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+ * real NMI signal was received:
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+ */
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+ if (!(v & ARCH_P4_UNFLAGGED_BIT))
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return 1;
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return 0;
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