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@@ -184,6 +184,7 @@
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#define DEV_HAS_PAUSEFRAME_TX_V1 0x08000 /* device supports tx pause frames version 1 */
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#define DEV_HAS_PAUSEFRAME_TX_V1 0x08000 /* device supports tx pause frames version 1 */
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#define DEV_HAS_PAUSEFRAME_TX_V2 0x10000 /* device supports tx pause frames version 2 */
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#define DEV_HAS_PAUSEFRAME_TX_V2 0x10000 /* device supports tx pause frames version 2 */
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#define DEV_HAS_PAUSEFRAME_TX_V3 0x20000 /* device supports tx pause frames version 3 */
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#define DEV_HAS_PAUSEFRAME_TX_V3 0x20000 /* device supports tx pause frames version 3 */
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+#define DEV_NEED_TX_LIMIT 0x40000 /* device needs to limit tx */
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enum {
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enum {
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NvRegIrqStatus = 0x000,
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NvRegIrqStatus = 0x000,
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@@ -635,6 +636,8 @@ union ring_type {
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#define NV_RESTART_TX 0x1
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#define NV_RESTART_TX 0x1
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#define NV_RESTART_RX 0x2
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#define NV_RESTART_RX 0x2
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+#define NV_TX_LIMIT_COUNT 16
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+
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/* statistics */
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/* statistics */
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struct nv_ethtool_str {
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struct nv_ethtool_str {
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char name[ETH_GSTRING_LEN];
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char name[ETH_GSTRING_LEN];
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@@ -743,6 +746,8 @@ struct nv_skb_map {
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struct sk_buff *skb;
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struct sk_buff *skb;
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dma_addr_t dma;
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dma_addr_t dma;
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unsigned int dma_len;
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unsigned int dma_len;
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+ struct ring_desc_ex *first_tx_desc;
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+ struct nv_skb_map *next_tx_ctx;
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};
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};
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/*
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/*
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@@ -827,6 +832,10 @@ struct fe_priv {
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union ring_type tx_ring;
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union ring_type tx_ring;
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u32 tx_flags;
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u32 tx_flags;
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int tx_ring_size;
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int tx_ring_size;
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+ int tx_limit;
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+ u32 tx_pkts_in_progress;
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+ struct nv_skb_map *tx_change_owner;
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+ struct nv_skb_map *tx_end_flip;
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int tx_stop;
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int tx_stop;
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/* vlan fields */
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/* vlan fields */
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@@ -1707,6 +1716,9 @@ static void nv_init_tx(struct net_device *dev)
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np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
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np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
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np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
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np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
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np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
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np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
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+ np->tx_pkts_in_progress = 0;
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+ np->tx_change_owner = NULL;
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+ np->tx_end_flip = NULL;
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for (i = 0; i < np->tx_ring_size; i++) {
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for (i = 0; i < np->tx_ring_size; i++) {
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
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@@ -1720,6 +1732,9 @@ static void nv_init_tx(struct net_device *dev)
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}
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}
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np->tx_skb[i].skb = NULL;
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np->tx_skb[i].skb = NULL;
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np->tx_skb[i].dma = 0;
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np->tx_skb[i].dma = 0;
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+ np->tx_skb[i].dma_len = 0;
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+ np->tx_skb[i].first_tx_desc = NULL;
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+ np->tx_skb[i].next_tx_ctx = NULL;
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}
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}
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}
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}
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@@ -1771,7 +1786,14 @@ static void nv_drain_tx(struct net_device *dev)
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}
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}
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if (nv_release_txskb(dev, &np->tx_skb[i]))
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if (nv_release_txskb(dev, &np->tx_skb[i]))
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dev->stats.tx_dropped++;
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dev->stats.tx_dropped++;
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+ np->tx_skb[i].dma = 0;
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+ np->tx_skb[i].dma_len = 0;
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+ np->tx_skb[i].first_tx_desc = NULL;
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+ np->tx_skb[i].next_tx_ctx = NULL;
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}
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}
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+ np->tx_pkts_in_progress = 0;
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+ np->tx_change_owner = NULL;
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+ np->tx_end_flip = NULL;
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}
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}
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static void nv_drain_rx(struct net_device *dev)
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static void nv_drain_rx(struct net_device *dev)
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@@ -1948,6 +1970,7 @@ static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
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struct ring_desc_ex* start_tx;
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struct ring_desc_ex* start_tx;
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struct ring_desc_ex* prev_tx;
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struct ring_desc_ex* prev_tx;
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struct nv_skb_map* prev_tx_ctx;
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struct nv_skb_map* prev_tx_ctx;
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+ struct nv_skb_map* start_tx_ctx;
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/* add fragments to entries count */
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/* add fragments to entries count */
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for (i = 0; i < fragments; i++) {
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for (i = 0; i < fragments; i++) {
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@@ -1965,6 +1988,7 @@ static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
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}
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}
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start_tx = put_tx = np->put_tx.ex;
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start_tx = put_tx = np->put_tx.ex;
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+ start_tx_ctx = np->put_tx_ctx;
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/* setup the header buffer */
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/* setup the header buffer */
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do {
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do {
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@@ -2037,6 +2061,26 @@ static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
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spin_lock_irq(&np->lock);
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spin_lock_irq(&np->lock);
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+ if (np->tx_limit) {
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+ /* Limit the number of outstanding tx. Setup all fragments, but
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+ * do not set the VALID bit on the first descriptor. Save a pointer
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+ * to that descriptor and also for next skb_map element.
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+ */
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+
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+ if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
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+ if (!np->tx_change_owner)
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+ np->tx_change_owner = start_tx_ctx;
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+
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+ /* remove VALID bit */
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+ tx_flags &= ~NV_TX2_VALID;
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+ start_tx_ctx->first_tx_desc = start_tx;
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+ start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
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+ np->tx_end_flip = np->put_tx_ctx;
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+ } else {
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+ np->tx_pkts_in_progress++;
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+ }
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+ }
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+
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/* set tx flags */
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/* set tx flags */
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start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
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start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
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np->put_tx.ex = put_tx;
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np->put_tx.ex = put_tx;
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@@ -2060,6 +2104,25 @@ static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
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return NETDEV_TX_OK;
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return NETDEV_TX_OK;
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}
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}
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+static inline void nv_tx_flip_ownership(struct net_device *dev)
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+{
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+ struct fe_priv *np = netdev_priv(dev);
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+
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+ np->tx_pkts_in_progress--;
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+ if (np->tx_change_owner) {
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+ __le32 flaglen = le32_to_cpu(np->tx_change_owner->first_tx_desc->flaglen);
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+ flaglen |= NV_TX2_VALID;
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+ np->tx_change_owner->first_tx_desc->flaglen = cpu_to_le32(flaglen);
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+ np->tx_pkts_in_progress++;
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+
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+ np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
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+ if (np->tx_change_owner == np->tx_end_flip)
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+ np->tx_change_owner = NULL;
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+
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+ writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
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+ }
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+}
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+
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/*
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/*
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* nv_tx_done: check for completed packets, release the skbs.
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* nv_tx_done: check for completed packets, release the skbs.
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*
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*
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@@ -2147,6 +2210,10 @@ static void nv_tx_done_optimized(struct net_device *dev, int limit)
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dev->stats.tx_packets++;
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dev->stats.tx_packets++;
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dev_kfree_skb_any(np->get_tx_ctx->skb);
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dev_kfree_skb_any(np->get_tx_ctx->skb);
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np->get_tx_ctx->skb = NULL;
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np->get_tx_ctx->skb = NULL;
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+
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+ if (np->tx_limit) {
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+ nv_tx_flip_ownership(dev);
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+ }
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}
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}
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if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
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if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
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np->get_tx.ex = np->first_tx.ex;
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np->get_tx.ex = np->first_tx.ex;
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@@ -5333,6 +5400,21 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
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np->need_linktimer = 0;
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np->need_linktimer = 0;
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}
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}
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+ /* Limit the number of tx's outstanding for hw bug */
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+ if (id->driver_data & DEV_NEED_TX_LIMIT) {
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+ np->tx_limit = 1;
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+ if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
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+ id->device == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
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+ id->device == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
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+ id->device == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
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+ id->device == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
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+ id->device == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
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+ id->device == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
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+ id->device == PCI_DEVICE_ID_NVIDIA_NVENET_39) &&
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+ pci_dev->revision >= 0xA2)
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+ np->tx_limit = 0;
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+ }
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+
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/* clear phy state and temporarily halt phy interrupts */
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/* clear phy state and temporarily halt phy interrupts */
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writel(0, base + NvRegMIIMask);
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writel(0, base + NvRegMIIMask);
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phystate = readl(base + NvRegAdapterControl);
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phystate = readl(base + NvRegAdapterControl);
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@@ -5563,19 +5645,19 @@ static struct pci_device_id pci_tbl[] = {
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},
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},
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{ /* CK804 Ethernet Controller */
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{ /* CK804 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
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- .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
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+ .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
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},
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},
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{ /* CK804 Ethernet Controller */
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{ /* CK804 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
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- .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
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+ .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
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},
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},
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{ /* MCP04 Ethernet Controller */
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{ /* MCP04 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
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- .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
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+ .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
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},
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},
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{ /* MCP04 Ethernet Controller */
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{ /* MCP04 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
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- .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
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+ .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
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},
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},
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{ /* MCP51 Ethernet Controller */
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{ /* MCP51 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
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@@ -5587,11 +5669,11 @@ static struct pci_device_id pci_tbl[] = {
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},
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},
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{ /* MCP55 Ethernet Controller */
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{ /* MCP55 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
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- .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
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+ .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
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},
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},
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{ /* MCP55 Ethernet Controller */
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{ /* MCP55 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
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- .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
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+ .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
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},
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},
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{ /* MCP61 Ethernet Controller */
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{ /* MCP61 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
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@@ -5611,19 +5693,19 @@ static struct pci_device_id pci_tbl[] = {
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},
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},
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{ /* MCP65 Ethernet Controller */
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{ /* MCP65 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
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- .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
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+ .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT,
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},
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},
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{ /* MCP65 Ethernet Controller */
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{ /* MCP65 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
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- .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
|
|
|
|
|
|
+ .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT,
|
|
},
|
|
},
|
|
{ /* MCP65 Ethernet Controller */
|
|
{ /* MCP65 Ethernet Controller */
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
|
|
- .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
|
|
|
|
|
|
+ .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT,
|
|
},
|
|
},
|
|
{ /* MCP65 Ethernet Controller */
|
|
{ /* MCP65 Ethernet Controller */
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
|
|
- .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
|
|
|
|
|
|
+ .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT,
|
|
},
|
|
},
|
|
{ /* MCP67 Ethernet Controller */
|
|
{ /* MCP67 Ethernet Controller */
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
|
|
@@ -5659,35 +5741,35 @@ static struct pci_device_id pci_tbl[] = {
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},
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|
},
|
|
{ /* MCP77 Ethernet Controller */
|
|
{ /* MCP77 Ethernet Controller */
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32),
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32),
|
|
- .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
|
|
|
|
|
|
+ .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
|
|
},
|
|
},
|
|
{ /* MCP77 Ethernet Controller */
|
|
{ /* MCP77 Ethernet Controller */
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33),
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33),
|
|
- .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
|
|
|
|
|
|
+ .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
|
|
},
|
|
},
|
|
{ /* MCP77 Ethernet Controller */
|
|
{ /* MCP77 Ethernet Controller */
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34),
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34),
|
|
- .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
|
|
|
|
|
|
+ .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
|
|
},
|
|
},
|
|
{ /* MCP77 Ethernet Controller */
|
|
{ /* MCP77 Ethernet Controller */
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
|
|
- .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
|
|
|
|
|
|
+ .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
|
|
},
|
|
},
|
|
{ /* MCP79 Ethernet Controller */
|
|
{ /* MCP79 Ethernet Controller */
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
|
|
- .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
|
|
|
|
|
|
+ .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
|
|
},
|
|
},
|
|
{ /* MCP79 Ethernet Controller */
|
|
{ /* MCP79 Ethernet Controller */
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
|
|
- .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
|
|
|
|
|
|
+ .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
|
|
},
|
|
},
|
|
{ /* MCP79 Ethernet Controller */
|
|
{ /* MCP79 Ethernet Controller */
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
|
|
- .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
|
|
|
|
|
|
+ .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
|
|
},
|
|
},
|
|
{ /* MCP79 Ethernet Controller */
|
|
{ /* MCP79 Ethernet Controller */
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
|
|
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
|
|
- .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
|
|
|
|
|
|
+ .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
|
|
},
|
|
},
|
|
{0,},
|
|
{0,},
|
|
};
|
|
};
|