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@@ -17,11 +17,11 @@
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#include <linux/interrupt.h>
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#include <linux/clockchips.h>
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#include <linux/sched.h>
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-#include <linux/cnt32_to_63.h>
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#include <asm/div64.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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+#include <asm/sched_clock.h>
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#include <mach/regs-ost.h>
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/*
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@@ -32,29 +32,18 @@
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* long as there is always less than 582 seconds between successive
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* calls to sched_clock() which should always be the case in practice.
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*/
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+static DEFINE_CLOCK_DATA(cd);
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-#define OSCR2NS_SCALE_FACTOR 10
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-
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-static unsigned long oscr2ns_scale;
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-
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-static void __init set_oscr2ns_scale(unsigned long oscr_rate)
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+unsigned long long notrace sched_clock(void)
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{
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- unsigned long long v = 1000000000ULL << OSCR2NS_SCALE_FACTOR;
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- do_div(v, oscr_rate);
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- oscr2ns_scale = v;
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- /*
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- * We want an even value to automatically clear the top bit
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- * returned by cnt32_to_63() without an additional run time
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- * instruction. So if the LSB is 1 then round it up.
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- */
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- if (oscr2ns_scale & 1)
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- oscr2ns_scale++;
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+ u32 cyc = OSCR;
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+ return cyc_to_sched_clock(&cd, cyc, (u32)~0);
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}
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-unsigned long long notrace sched_clock(void)
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+static void notrace pxa_update_sched_clock(void)
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{
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- unsigned long long v = cnt32_to_63(OSCR);
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- return (v * oscr2ns_scale) >> OSCR2NS_SCALE_FACTOR;
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+ u32 cyc = OSCR;
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+ update_sched_clock(&cd, cyc, (u32)~0);
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}
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@@ -144,7 +133,7 @@ static void __init pxa_timer_init(void)
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OIER = 0;
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OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
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- set_oscr2ns_scale(clock_tick_rate);
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+ init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate);
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ckevt_pxa_osmr0.mult =
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div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
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