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@@ -7,7 +7,7 @@
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*/
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/* This file shoule be up to date with:
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- * - Revision C, July 16, 2007; ADSP-BF549 Silicon Anomaly List
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+ * - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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@@ -26,47 +26,59 @@
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/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
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#define ANOMALY_05000272 (1)
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/* False Hardware Error Exception when ISR context is not restored */
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-#define ANOMALY_05000281 (1)
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+#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
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/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
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-#define ANOMALY_05000304 (1)
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+#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
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/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
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#define ANOMALY_05000310 (1)
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/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
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-#define ANOMALY_05000312 (1)
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+#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
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/* TWI Slave Boot Mode Is Not Functional */
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-#define ANOMALY_05000324 (1)
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+#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
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/* External FIFO Boot Mode Is Not Functional */
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-#define ANOMALY_05000325 (1)
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+#define ANOMALY_05000325 (__SILICON_REVISION__ < 1)
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/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
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-#define ANOMALY_05000327 (1)
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+#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
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/* Incorrect Access of OTP_STATUS During otp_write() Function */
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-#define ANOMALY_05000328 (1)
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+#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
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/* Synchronous Burst Flash Boot Mode Is Not Functional */
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-#define ANOMALY_05000329 (1)
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+#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
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/* Host DMA Boot Mode Is Not Functional */
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-#define ANOMALY_05000330 (1)
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+#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
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/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
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-#define ANOMALY_05000334 (1)
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+#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
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/* Inadequate Rotary Debounce Logic Duration */
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-#define ANOMALY_05000335 (1)
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+#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
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/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
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-#define ANOMALY_05000336 (1)
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+#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
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/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
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-#define ANOMALY_05000337 (1)
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+#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
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/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
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-#define ANOMALY_05000338 (1)
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+#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
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/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
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-#define ANOMALY_05000340 (1)
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+#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
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/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
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-#define ANOMALY_05000344 (1)
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+#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
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/* USB Calibration Value Is Not Intialized */
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-#define ANOMALY_05000346 (1)
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+#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
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/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
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-#define ANOMALY_05000347 (1)
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+#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
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/* Data Lost when Core Reads SDH Data FIFO */
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-#define ANOMALY_05000349 (1)
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+#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
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/* PLL Status Register Is Inaccurate */
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-#define ANOMALY_05000351 (1)
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+#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
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+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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+#define ANOMALY_05000357 (1)
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+/* External Memory Read Access Hangs Core With PLL Bypass */
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+#define ANOMALY_05000360 (1)
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+/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
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+#define ANOMALY_05000365 (1)
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+/* Addressing Conflict between Boot ROM and Asynchronous Memory */
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+#define ANOMALY_05000369 (1)
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+/* Mobile DDR Operation Not Functional */
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+#define ANOMALY_05000377 (1)
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+/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
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+#define ANOMALY_05000378 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000125 (0)
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Mike Frysinger