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@@ -3181,15 +3181,6 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
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/* For PCH output, training FDI link */
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dev_priv->display.fdi_link_train(crtc);
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- /* XXX: pch pll's can be enabled any time before we enable the PCH
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- * transcoder, and we actually should do this to not upset any PCH
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- * transcoder that already use the clock when we share it.
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- *
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- * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
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- * unconditionally resets the pll - we need that to have the right LVDS
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- * enable sequence. */
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- ironlake_enable_pch_pll(intel_crtc);
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-
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lpt_program_iclkip(crtc);
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/* set transcoder timing, panel must allow it */
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