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@@ -37,15 +37,6 @@ struct pebs_record_nhm {
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u64 status, dla, dse, lat;
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};
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-/*
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- * Bits in the debugctlmsr controlling branch tracing.
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- */
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-#define X86_DEBUGCTL_TR (1 << 6)
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-#define X86_DEBUGCTL_BTS (1 << 7)
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-#define X86_DEBUGCTL_BTINT (1 << 8)
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-#define X86_DEBUGCTL_BTS_OFF_OS (1 << 9)
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-#define X86_DEBUGCTL_BTS_OFF_USR (1 << 10)
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-
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/*
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* A debug store configuration.
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*
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@@ -193,15 +184,15 @@ static void intel_pmu_enable_bts(u64 config)
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debugctlmsr = get_debugctlmsr();
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- debugctlmsr |= X86_DEBUGCTL_TR;
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- debugctlmsr |= X86_DEBUGCTL_BTS;
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- debugctlmsr |= X86_DEBUGCTL_BTINT;
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+ debugctlmsr |= DEBUGCTLMSR_TR;
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+ debugctlmsr |= DEBUGCTLMSR_BTS;
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+ debugctlmsr |= DEBUGCTLMSR_BTINT;
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if (!(config & ARCH_PERFMON_EVENTSEL_OS))
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- debugctlmsr |= X86_DEBUGCTL_BTS_OFF_OS;
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+ debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
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if (!(config & ARCH_PERFMON_EVENTSEL_USR))
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- debugctlmsr |= X86_DEBUGCTL_BTS_OFF_USR;
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+ debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
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update_debugctlmsr(debugctlmsr);
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}
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@@ -217,8 +208,8 @@ static void intel_pmu_disable_bts(void)
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debugctlmsr = get_debugctlmsr();
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debugctlmsr &=
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- ~(X86_DEBUGCTL_TR | X86_DEBUGCTL_BTS | X86_DEBUGCTL_BTINT |
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- X86_DEBUGCTL_BTS_OFF_OS | X86_DEBUGCTL_BTS_OFF_USR);
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+ ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
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+ DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
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update_debugctlmsr(debugctlmsr);
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}
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