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@@ -182,16 +182,6 @@ struct hdmi_reg { u16 idx; };
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#define HDMI_TXPHY_POWER_CTRL HDMI_REG(0x8)
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#define HDMI_TXPHY_PAD_CFG_CTRL HDMI_REG(0xC)
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-/* HDMI EDID Length */
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-#define HDMI_EDID_MAX_LENGTH 256
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-#define EDID_TIMING_DESCRIPTOR_SIZE 0x12
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-#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
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-#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
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-#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
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-#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
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-
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-#define OMAP_HDMI_TIMINGS_NB 34
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-
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#define REG_FLD_MOD(base, idx, val, start, end) \
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hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
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val, start, end))
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