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@@ -742,13 +742,14 @@ static struct {
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*/
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*/
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static void radeon_clear_box(drm_radeon_private_t * dev_priv,
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static void radeon_clear_box(drm_radeon_private_t * dev_priv,
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+ struct drm_radeon_master_private *master_priv,
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int x, int y, int w, int h, int r, int g, int b)
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int x, int y, int w, int h, int r, int g, int b)
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{
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{
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u32 color;
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u32 color;
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RING_LOCALS;
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RING_LOCALS;
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- x += dev_priv->sarea_priv->boxes[0].x1;
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- y += dev_priv->sarea_priv->boxes[0].y1;
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+ x += master_priv->sarea_priv->boxes[0].x1;
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+ y += master_priv->sarea_priv->boxes[0].y1;
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switch (dev_priv->color_fmt) {
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switch (dev_priv->color_fmt) {
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case RADEON_COLOR_FORMAT_RGB565:
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case RADEON_COLOR_FORMAT_RGB565:
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@@ -776,7 +777,7 @@ static void radeon_clear_box(drm_radeon_private_t * dev_priv,
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RADEON_GMC_SRC_DATATYPE_COLOR |
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RADEON_GMC_SRC_DATATYPE_COLOR |
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RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS);
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RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS);
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- if (dev_priv->sarea_priv->pfCurrentPage == 1) {
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+ if (master_priv->sarea_priv->pfCurrentPage == 1) {
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OUT_RING(dev_priv->front_pitch_offset);
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OUT_RING(dev_priv->front_pitch_offset);
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} else {
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} else {
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OUT_RING(dev_priv->back_pitch_offset);
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OUT_RING(dev_priv->back_pitch_offset);
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@@ -790,7 +791,7 @@ static void radeon_clear_box(drm_radeon_private_t * dev_priv,
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ADVANCE_RING();
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ADVANCE_RING();
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}
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}
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-static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv)
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+static void radeon_cp_performance_boxes(drm_radeon_private_t *dev_priv, struct drm_radeon_master_private *master_priv)
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{
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{
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/* Collapse various things into a wait flag -- trying to
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/* Collapse various things into a wait flag -- trying to
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* guess if userspase slept -- better just to have them tell us.
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* guess if userspase slept -- better just to have them tell us.
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@@ -807,12 +808,12 @@ static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv)
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/* Purple box for page flipping
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/* Purple box for page flipping
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*/
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*/
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if (dev_priv->stats.boxes & RADEON_BOX_FLIP)
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if (dev_priv->stats.boxes & RADEON_BOX_FLIP)
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- radeon_clear_box(dev_priv, 4, 4, 8, 8, 255, 0, 255);
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+ radeon_clear_box(dev_priv, master_priv, 4, 4, 8, 8, 255, 0, 255);
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/* Red box if we have to wait for idle at any point
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/* Red box if we have to wait for idle at any point
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*/
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*/
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if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE)
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if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE)
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- radeon_clear_box(dev_priv, 16, 4, 8, 8, 255, 0, 0);
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+ radeon_clear_box(dev_priv, master_priv, 16, 4, 8, 8, 255, 0, 0);
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/* Blue box: lost context?
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/* Blue box: lost context?
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*/
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*/
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@@ -820,12 +821,12 @@ static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv)
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/* Yellow box for texture swaps
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/* Yellow box for texture swaps
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*/
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*/
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if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD)
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if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD)
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- radeon_clear_box(dev_priv, 40, 4, 8, 8, 255, 255, 0);
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+ radeon_clear_box(dev_priv, master_priv, 40, 4, 8, 8, 255, 255, 0);
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/* Green box if hardware never idles (as far as we can tell)
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/* Green box if hardware never idles (as far as we can tell)
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*/
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*/
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if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE))
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if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE))
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- radeon_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0);
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+ radeon_clear_box(dev_priv, master_priv, 64, 4, 8, 8, 0, 255, 0);
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/* Draw bars indicating number of buffers allocated
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/* Draw bars indicating number of buffers allocated
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* (not a great measure, easily confused)
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* (not a great measure, easily confused)
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@@ -834,7 +835,7 @@ static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv)
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if (dev_priv->stats.requested_bufs > 100)
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if (dev_priv->stats.requested_bufs > 100)
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dev_priv->stats.requested_bufs = 100;
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dev_priv->stats.requested_bufs = 100;
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- radeon_clear_box(dev_priv, 4, 16,
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+ radeon_clear_box(dev_priv, master_priv, 4, 16,
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dev_priv->stats.requested_bufs, 4,
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dev_priv->stats.requested_bufs, 4,
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196, 128, 128);
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196, 128, 128);
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}
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}
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@@ -848,11 +849,13 @@ static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv)
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*/
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*/
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static void radeon_cp_dispatch_clear(struct drm_device * dev,
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static void radeon_cp_dispatch_clear(struct drm_device * dev,
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+ struct drm_master *master,
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drm_radeon_clear_t * clear,
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drm_radeon_clear_t * clear,
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drm_radeon_clear_rect_t * depth_boxes)
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drm_radeon_clear_rect_t * depth_boxes)
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{
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_radeon_private_t *dev_priv = dev->dev_private;
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- drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
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+ struct drm_radeon_master_private *master_priv = master->driver_priv;
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+ drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
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drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear;
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drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear;
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int nbox = sarea_priv->nbox;
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int nbox = sarea_priv->nbox;
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struct drm_clip_rect *pbox = sarea_priv->boxes;
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struct drm_clip_rect *pbox = sarea_priv->boxes;
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@@ -864,7 +867,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
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dev_priv->stats.clears++;
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dev_priv->stats.clears++;
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- if (dev_priv->sarea_priv->pfCurrentPage == 1) {
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+ if (sarea_priv->pfCurrentPage == 1) {
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unsigned int tmp = flags;
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unsigned int tmp = flags;
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flags &= ~(RADEON_FRONT | RADEON_BACK);
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flags &= ~(RADEON_FRONT | RADEON_BACK);
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@@ -890,7 +893,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
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/* Make sure we restore the 3D state next time.
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/* Make sure we restore the 3D state next time.
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*/
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*/
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- dev_priv->sarea_priv->ctx_owner = 0;
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+ sarea_priv->ctx_owner = 0;
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for (i = 0; i < nbox; i++) {
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for (i = 0; i < nbox; i++) {
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int x = pbox[i].x1;
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int x = pbox[i].x1;
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@@ -967,7 +970,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
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/* Make sure we restore the 3D state next time.
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/* Make sure we restore the 3D state next time.
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* we haven't touched any "normal" state - still need this?
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* we haven't touched any "normal" state - still need this?
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*/
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*/
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- dev_priv->sarea_priv->ctx_owner = 0;
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+ sarea_priv->ctx_owner = 0;
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if ((dev_priv->flags & RADEON_HAS_HIERZ)
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if ((dev_priv->flags & RADEON_HAS_HIERZ)
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&& (flags & RADEON_USE_HIERZ)) {
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&& (flags & RADEON_USE_HIERZ)) {
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@@ -1214,7 +1217,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
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/* Make sure we restore the 3D state next time.
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/* Make sure we restore the 3D state next time.
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*/
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*/
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- dev_priv->sarea_priv->ctx_owner = 0;
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+ sarea_priv->ctx_owner = 0;
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for (i = 0; i < nbox; i++) {
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for (i = 0; i < nbox; i++) {
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@@ -1285,7 +1288,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
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/* Make sure we restore the 3D state next time.
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/* Make sure we restore the 3D state next time.
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*/
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*/
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- dev_priv->sarea_priv->ctx_owner = 0;
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+ sarea_priv->ctx_owner = 0;
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for (i = 0; i < nbox; i++) {
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for (i = 0; i < nbox; i++) {
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@@ -1328,20 +1331,21 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
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* wait on this value before performing the clear ioctl. We
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* wait on this value before performing the clear ioctl. We
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* need this because the card's so damned fast...
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* need this because the card's so damned fast...
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*/
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*/
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- dev_priv->sarea_priv->last_clear++;
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+ sarea_priv->last_clear++;
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BEGIN_RING(4);
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BEGIN_RING(4);
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- RADEON_CLEAR_AGE(dev_priv->sarea_priv->last_clear);
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+ RADEON_CLEAR_AGE(sarea_priv->last_clear);
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RADEON_WAIT_UNTIL_IDLE();
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RADEON_WAIT_UNTIL_IDLE();
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ADVANCE_RING();
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ADVANCE_RING();
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}
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}
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-static void radeon_cp_dispatch_swap(struct drm_device * dev)
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+static void radeon_cp_dispatch_swap(struct drm_device *dev, struct drm_master *master)
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{
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_radeon_private_t *dev_priv = dev->dev_private;
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- drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
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+ struct drm_radeon_master_private *master_priv = master->driver_priv;
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+ drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
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int nbox = sarea_priv->nbox;
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int nbox = sarea_priv->nbox;
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struct drm_clip_rect *pbox = sarea_priv->boxes;
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struct drm_clip_rect *pbox = sarea_priv->boxes;
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int i;
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int i;
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@@ -1351,7 +1355,7 @@ static void radeon_cp_dispatch_swap(struct drm_device * dev)
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/* Do some trivial performance monitoring...
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/* Do some trivial performance monitoring...
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*/
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*/
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if (dev_priv->do_boxes)
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if (dev_priv->do_boxes)
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- radeon_cp_performance_boxes(dev_priv);
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+ radeon_cp_performance_boxes(dev_priv, master_priv);
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/* Wait for the 3D stream to idle before dispatching the bitblt.
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/* Wait for the 3D stream to idle before dispatching the bitblt.
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* This will prevent data corruption between the two streams.
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* This will prevent data corruption between the two streams.
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@@ -1385,7 +1389,7 @@ static void radeon_cp_dispatch_swap(struct drm_device * dev)
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/* Make this work even if front & back are flipped:
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/* Make this work even if front & back are flipped:
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*/
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*/
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OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1));
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OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1));
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- if (dev_priv->sarea_priv->pfCurrentPage == 0) {
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+ if (sarea_priv->pfCurrentPage == 0) {
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OUT_RING(dev_priv->back_pitch_offset);
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OUT_RING(dev_priv->back_pitch_offset);
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OUT_RING(dev_priv->front_pitch_offset);
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OUT_RING(dev_priv->front_pitch_offset);
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} else {
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} else {
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@@ -1405,31 +1409,32 @@ static void radeon_cp_dispatch_swap(struct drm_device * dev)
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* throttle the framerate by waiting for this value before
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* throttle the framerate by waiting for this value before
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* performing the swapbuffer ioctl.
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* performing the swapbuffer ioctl.
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*/
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*/
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- dev_priv->sarea_priv->last_frame++;
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+ sarea_priv->last_frame++;
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BEGIN_RING(4);
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BEGIN_RING(4);
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- RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
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+ RADEON_FRAME_AGE(sarea_priv->last_frame);
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RADEON_WAIT_UNTIL_2D_IDLE();
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RADEON_WAIT_UNTIL_2D_IDLE();
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ADVANCE_RING();
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ADVANCE_RING();
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}
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}
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-static void radeon_cp_dispatch_flip(struct drm_device * dev)
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+void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master)
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{
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_radeon_private_t *dev_priv = dev->dev_private;
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- struct drm_sarea *sarea = (struct drm_sarea *) dev_priv->sarea->handle;
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- int offset = (dev_priv->sarea_priv->pfCurrentPage == 1)
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+ struct drm_radeon_master_private *master_priv = master->driver_priv;
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+ struct drm_sarea *sarea = (struct drm_sarea *)master_priv->sarea->handle;
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+ int offset = (master_priv->sarea_priv->pfCurrentPage == 1)
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? dev_priv->front_offset : dev_priv->back_offset;
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? dev_priv->front_offset : dev_priv->back_offset;
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RING_LOCALS;
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RING_LOCALS;
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DRM_DEBUG("pfCurrentPage=%d\n",
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DRM_DEBUG("pfCurrentPage=%d\n",
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- dev_priv->sarea_priv->pfCurrentPage);
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+ master_priv->sarea_priv->pfCurrentPage);
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/* Do some trivial performance monitoring...
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/* Do some trivial performance monitoring...
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*/
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*/
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if (dev_priv->do_boxes) {
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if (dev_priv->do_boxes) {
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dev_priv->stats.boxes |= RADEON_BOX_FLIP;
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dev_priv->stats.boxes |= RADEON_BOX_FLIP;
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- radeon_cp_performance_boxes(dev_priv);
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+ radeon_cp_performance_boxes(dev_priv, master_priv);
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}
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}
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/* Update the frame offsets for both CRTCs
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/* Update the frame offsets for both CRTCs
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@@ -1441,7 +1446,7 @@ static void radeon_cp_dispatch_flip(struct drm_device * dev)
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((sarea->frame.y * dev_priv->front_pitch +
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((sarea->frame.y * dev_priv->front_pitch +
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sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7)
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sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7)
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+ offset);
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+ offset);
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- OUT_RING_REG(RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base
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+ OUT_RING_REG(RADEON_CRTC2_OFFSET, master_priv->sarea_priv->crtc2_base
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+ offset);
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+ offset);
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ADVANCE_RING();
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ADVANCE_RING();
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@@ -1450,13 +1455,13 @@ static void radeon_cp_dispatch_flip(struct drm_device * dev)
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* throttle the framerate by waiting for this value before
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* throttle the framerate by waiting for this value before
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* performing the swapbuffer ioctl.
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* performing the swapbuffer ioctl.
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*/
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*/
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- dev_priv->sarea_priv->last_frame++;
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- dev_priv->sarea_priv->pfCurrentPage =
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- 1 - dev_priv->sarea_priv->pfCurrentPage;
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+ master_priv->sarea_priv->last_frame++;
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+ master_priv->sarea_priv->pfCurrentPage =
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+ 1 - master_priv->sarea_priv->pfCurrentPage;
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BEGIN_RING(2);
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BEGIN_RING(2);
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- RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
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+ RADEON_FRAME_AGE(master_priv->sarea_priv->last_frame);
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ADVANCE_RING();
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ADVANCE_RING();
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}
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}
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@@ -1494,11 +1499,13 @@ typedef struct {
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} drm_radeon_tcl_prim_t;
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} drm_radeon_tcl_prim_t;
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static void radeon_cp_dispatch_vertex(struct drm_device * dev,
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static void radeon_cp_dispatch_vertex(struct drm_device * dev,
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+ struct drm_file *file_priv,
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struct drm_buf * buf,
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struct drm_buf * buf,
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drm_radeon_tcl_prim_t * prim)
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drm_radeon_tcl_prim_t * prim)
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{
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_radeon_private_t *dev_priv = dev->dev_private;
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- drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
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+ struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
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+ drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
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|
int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
|
|
int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
|
|
int numverts = (int)prim->numverts;
|
|
int numverts = (int)prim->numverts;
|
|
int nbox = sarea_priv->nbox;
|
|
int nbox = sarea_priv->nbox;
|
|
@@ -1539,13 +1546,14 @@ static void radeon_cp_dispatch_vertex(struct drm_device * dev,
|
|
} while (i < nbox);
|
|
} while (i < nbox);
|
|
}
|
|
}
|
|
|
|
|
|
-static void radeon_cp_discard_buffer(struct drm_device * dev, struct drm_buf * buf)
|
|
|
|
|
|
+static void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf)
|
|
{
|
|
{
|
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
|
|
+ struct drm_radeon_master_private *master_priv = master->driver_priv;
|
|
drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
|
|
drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
|
|
RING_LOCALS;
|
|
RING_LOCALS;
|
|
|
|
|
|
- buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
|
|
|
|
|
|
+ buf_priv->age = ++master_priv->sarea_priv->last_dispatch;
|
|
|
|
|
|
/* Emit the vertex buffer age */
|
|
/* Emit the vertex buffer age */
|
|
BEGIN_RING(2);
|
|
BEGIN_RING(2);
|
|
@@ -1590,12 +1598,14 @@ static void radeon_cp_dispatch_indirect(struct drm_device * dev,
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
-static void radeon_cp_dispatch_indices(struct drm_device * dev,
|
|
|
|
|
|
+static void radeon_cp_dispatch_indices(struct drm_device *dev,
|
|
|
|
+ struct drm_master *master,
|
|
struct drm_buf * elt_buf,
|
|
struct drm_buf * elt_buf,
|
|
drm_radeon_tcl_prim_t * prim)
|
|
drm_radeon_tcl_prim_t * prim)
|
|
{
|
|
{
|
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
- drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
|
|
|
|
|
+ struct drm_radeon_master_private *master_priv = master->driver_priv;
|
|
|
|
+ drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
|
|
int offset = dev_priv->gart_buffers_offset + prim->offset;
|
|
int offset = dev_priv->gart_buffers_offset + prim->offset;
|
|
u32 *data;
|
|
u32 *data;
|
|
int dwords;
|
|
int dwords;
|
|
@@ -1870,7 +1880,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
|
|
ADVANCE_RING();
|
|
ADVANCE_RING();
|
|
COMMIT_RING();
|
|
COMMIT_RING();
|
|
|
|
|
|
- radeon_cp_discard_buffer(dev, buf);
|
|
|
|
|
|
+ radeon_cp_discard_buffer(dev, file_priv->master, buf);
|
|
|
|
|
|
/* Update the input parameters for next time */
|
|
/* Update the input parameters for next time */
|
|
image->y += height;
|
|
image->y += height;
|
|
@@ -2110,7 +2120,8 @@ static int radeon_surface_free(struct drm_device *dev, void *data, struct drm_fi
|
|
static int radeon_cp_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
|
|
static int radeon_cp_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
|
|
{
|
|
{
|
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
- drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
|
|
|
|
|
+ struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
|
|
|
|
+ drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
|
|
drm_radeon_clear_t *clear = data;
|
|
drm_radeon_clear_t *clear = data;
|
|
drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
|
|
drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
|
|
DRM_DEBUG("\n");
|
|
DRM_DEBUG("\n");
|
|
@@ -2126,7 +2137,7 @@ static int radeon_cp_clear(struct drm_device *dev, void *data, struct drm_file *
|
|
sarea_priv->nbox * sizeof(depth_boxes[0])))
|
|
sarea_priv->nbox * sizeof(depth_boxes[0])))
|
|
return -EFAULT;
|
|
return -EFAULT;
|
|
|
|
|
|
- radeon_cp_dispatch_clear(dev, clear, depth_boxes);
|
|
|
|
|
|
+ radeon_cp_dispatch_clear(dev, file_priv->master, clear, depth_boxes);
|
|
|
|
|
|
COMMIT_RING();
|
|
COMMIT_RING();
|
|
return 0;
|
|
return 0;
|
|
@@ -2134,9 +2145,10 @@ static int radeon_cp_clear(struct drm_device *dev, void *data, struct drm_file *
|
|
|
|
|
|
/* Not sure why this isn't set all the time:
|
|
/* Not sure why this isn't set all the time:
|
|
*/
|
|
*/
|
|
-static int radeon_do_init_pageflip(struct drm_device * dev)
|
|
|
|
|
|
+static int radeon_do_init_pageflip(struct drm_device *dev, struct drm_master *master)
|
|
{
|
|
{
|
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
|
|
+ struct drm_radeon_master_private *master_priv = master->driver_priv;
|
|
RING_LOCALS;
|
|
RING_LOCALS;
|
|
|
|
|
|
DRM_DEBUG("\n");
|
|
DRM_DEBUG("\n");
|
|
@@ -2153,8 +2165,8 @@ static int radeon_do_init_pageflip(struct drm_device * dev)
|
|
|
|
|
|
dev_priv->page_flipping = 1;
|
|
dev_priv->page_flipping = 1;
|
|
|
|
|
|
- if (dev_priv->sarea_priv->pfCurrentPage != 1)
|
|
|
|
- dev_priv->sarea_priv->pfCurrentPage = 0;
|
|
|
|
|
|
+ if (master_priv->sarea_priv->pfCurrentPage != 1)
|
|
|
|
+ master_priv->sarea_priv->pfCurrentPage = 0;
|
|
|
|
|
|
return 0;
|
|
return 0;
|
|
}
|
|
}
|
|
@@ -2172,9 +2184,9 @@ static int radeon_cp_flip(struct drm_device *dev, void *data, struct drm_file *f
|
|
RING_SPACE_TEST_WITH_RETURN(dev_priv);
|
|
RING_SPACE_TEST_WITH_RETURN(dev_priv);
|
|
|
|
|
|
if (!dev_priv->page_flipping)
|
|
if (!dev_priv->page_flipping)
|
|
- radeon_do_init_pageflip(dev);
|
|
|
|
|
|
+ radeon_do_init_pageflip(dev, file_priv->master);
|
|
|
|
|
|
- radeon_cp_dispatch_flip(dev);
|
|
|
|
|
|
+ radeon_cp_dispatch_flip(dev, file_priv->master);
|
|
|
|
|
|
COMMIT_RING();
|
|
COMMIT_RING();
|
|
return 0;
|
|
return 0;
|
|
@@ -2183,7 +2195,9 @@ static int radeon_cp_flip(struct drm_device *dev, void *data, struct drm_file *f
|
|
static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *file_priv)
|
|
static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *file_priv)
|
|
{
|
|
{
|
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
- drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
|
|
|
|
|
+ struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
|
|
|
|
+ drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
|
|
|
|
+
|
|
DRM_DEBUG("\n");
|
|
DRM_DEBUG("\n");
|
|
|
|
|
|
LOCK_TEST_WITH_RETURN(dev, file_priv);
|
|
LOCK_TEST_WITH_RETURN(dev, file_priv);
|
|
@@ -2193,8 +2207,8 @@ static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *f
|
|
if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
|
|
if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
|
|
sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
|
|
sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
|
|
|
|
|
|
- radeon_cp_dispatch_swap(dev);
|
|
|
|
- dev_priv->sarea_priv->ctx_owner = 0;
|
|
|
|
|
|
+ radeon_cp_dispatch_swap(dev, file_priv->master);
|
|
|
|
+ sarea_priv->ctx_owner = 0;
|
|
|
|
|
|
COMMIT_RING();
|
|
COMMIT_RING();
|
|
return 0;
|
|
return 0;
|
|
@@ -2203,7 +2217,8 @@ static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *f
|
|
static int radeon_cp_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv)
|
|
static int radeon_cp_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv)
|
|
{
|
|
{
|
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
- drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
|
|
|
|
|
+ struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
|
|
|
|
+ drm_radeon_sarea_t *sarea_priv;
|
|
struct drm_device_dma *dma = dev->dma;
|
|
struct drm_device_dma *dma = dev->dma;
|
|
struct drm_buf *buf;
|
|
struct drm_buf *buf;
|
|
drm_radeon_vertex_t *vertex = data;
|
|
drm_radeon_vertex_t *vertex = data;
|
|
@@ -2211,6 +2226,8 @@ static int radeon_cp_vertex(struct drm_device *dev, void *data, struct drm_file
|
|
|
|
|
|
LOCK_TEST_WITH_RETURN(dev, file_priv);
|
|
LOCK_TEST_WITH_RETURN(dev, file_priv);
|
|
|
|
|
|
|
|
+ sarea_priv = master_priv->sarea_priv;
|
|
|
|
+
|
|
DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
|
|
DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
|
|
DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard);
|
|
DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard);
|
|
|
|
|
|
@@ -2263,13 +2280,13 @@ static int radeon_cp_vertex(struct drm_device *dev, void *data, struct drm_file
|
|
prim.finish = vertex->count; /* unused */
|
|
prim.finish = vertex->count; /* unused */
|
|
prim.prim = vertex->prim;
|
|
prim.prim = vertex->prim;
|
|
prim.numverts = vertex->count;
|
|
prim.numverts = vertex->count;
|
|
- prim.vc_format = dev_priv->sarea_priv->vc_format;
|
|
|
|
|
|
+ prim.vc_format = sarea_priv->vc_format;
|
|
|
|
|
|
- radeon_cp_dispatch_vertex(dev, buf, &prim);
|
|
|
|
|
|
+ radeon_cp_dispatch_vertex(dev, file_priv, buf, &prim);
|
|
}
|
|
}
|
|
|
|
|
|
if (vertex->discard) {
|
|
if (vertex->discard) {
|
|
- radeon_cp_discard_buffer(dev, buf);
|
|
|
|
|
|
+ radeon_cp_discard_buffer(dev, file_priv->master, buf);
|
|
}
|
|
}
|
|
|
|
|
|
COMMIT_RING();
|
|
COMMIT_RING();
|
|
@@ -2279,7 +2296,8 @@ static int radeon_cp_vertex(struct drm_device *dev, void *data, struct drm_file
|
|
static int radeon_cp_indices(struct drm_device *dev, void *data, struct drm_file *file_priv)
|
|
static int radeon_cp_indices(struct drm_device *dev, void *data, struct drm_file *file_priv)
|
|
{
|
|
{
|
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
- drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
|
|
|
|
|
+ struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
|
|
|
|
+ drm_radeon_sarea_t *sarea_priv;
|
|
struct drm_device_dma *dma = dev->dma;
|
|
struct drm_device_dma *dma = dev->dma;
|
|
struct drm_buf *buf;
|
|
struct drm_buf *buf;
|
|
drm_radeon_indices_t *elts = data;
|
|
drm_radeon_indices_t *elts = data;
|
|
@@ -2288,6 +2306,8 @@ static int radeon_cp_indices(struct drm_device *dev, void *data, struct drm_file
|
|
|
|
|
|
LOCK_TEST_WITH_RETURN(dev, file_priv);
|
|
LOCK_TEST_WITH_RETURN(dev, file_priv);
|
|
|
|
|
|
|
|
+ sarea_priv = master_priv->sarea_priv;
|
|
|
|
+
|
|
DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n",
|
|
DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n",
|
|
DRM_CURRENTPID, elts->idx, elts->start, elts->end,
|
|
DRM_CURRENTPID, elts->idx, elts->start, elts->end,
|
|
elts->discard);
|
|
elts->discard);
|
|
@@ -2353,11 +2373,11 @@ static int radeon_cp_indices(struct drm_device *dev, void *data, struct drm_file
|
|
prim.prim = elts->prim;
|
|
prim.prim = elts->prim;
|
|
prim.offset = 0; /* offset from start of dma buffers */
|
|
prim.offset = 0; /* offset from start of dma buffers */
|
|
prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
|
|
prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
|
|
- prim.vc_format = dev_priv->sarea_priv->vc_format;
|
|
|
|
|
|
+ prim.vc_format = sarea_priv->vc_format;
|
|
|
|
|
|
- radeon_cp_dispatch_indices(dev, buf, &prim);
|
|
|
|
|
|
+ radeon_cp_dispatch_indices(dev, file_priv->master, buf, &prim);
|
|
if (elts->discard) {
|
|
if (elts->discard) {
|
|
- radeon_cp_discard_buffer(dev, buf);
|
|
|
|
|
|
+ radeon_cp_discard_buffer(dev, file_priv->master, buf);
|
|
}
|
|
}
|
|
|
|
|
|
COMMIT_RING();
|
|
COMMIT_RING();
|
|
@@ -2468,7 +2488,7 @@ static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_fil
|
|
*/
|
|
*/
|
|
radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
|
|
radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
|
|
if (indirect->discard) {
|
|
if (indirect->discard) {
|
|
- radeon_cp_discard_buffer(dev, buf);
|
|
|
|
|
|
+ radeon_cp_discard_buffer(dev, file_priv->master, buf);
|
|
}
|
|
}
|
|
|
|
|
|
COMMIT_RING();
|
|
COMMIT_RING();
|
|
@@ -2478,7 +2498,8 @@ static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_fil
|
|
static int radeon_cp_vertex2(struct drm_device *dev, void *data, struct drm_file *file_priv)
|
|
static int radeon_cp_vertex2(struct drm_device *dev, void *data, struct drm_file *file_priv)
|
|
{
|
|
{
|
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
- drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
|
|
|
|
|
|
+ struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
|
|
|
|
+ drm_radeon_sarea_t *sarea_priv;
|
|
struct drm_device_dma *dma = dev->dma;
|
|
struct drm_device_dma *dma = dev->dma;
|
|
struct drm_buf *buf;
|
|
struct drm_buf *buf;
|
|
drm_radeon_vertex2_t *vertex = data;
|
|
drm_radeon_vertex2_t *vertex = data;
|
|
@@ -2487,6 +2508,8 @@ static int radeon_cp_vertex2(struct drm_device *dev, void *data, struct drm_file
|
|
|
|
|
|
LOCK_TEST_WITH_RETURN(dev, file_priv);
|
|
LOCK_TEST_WITH_RETURN(dev, file_priv);
|
|
|
|
|
|
|
|
+ sarea_priv = master_priv->sarea_priv;
|
|
|
|
+
|
|
DRM_DEBUG("pid=%d index=%d discard=%d\n",
|
|
DRM_DEBUG("pid=%d index=%d discard=%d\n",
|
|
DRM_CURRENTPID, vertex->idx, vertex->discard);
|
|
DRM_CURRENTPID, vertex->idx, vertex->discard);
|
|
|
|
|
|
@@ -2547,12 +2570,12 @@ static int radeon_cp_vertex2(struct drm_device *dev, void *data, struct drm_file
|
|
tclprim.offset = prim.numverts * 64;
|
|
tclprim.offset = prim.numverts * 64;
|
|
tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
|
|
tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
|
|
|
|
|
|
- radeon_cp_dispatch_indices(dev, buf, &tclprim);
|
|
|
|
|
|
+ radeon_cp_dispatch_indices(dev, file_priv->master, buf, &tclprim);
|
|
} else {
|
|
} else {
|
|
tclprim.numverts = prim.numverts;
|
|
tclprim.numverts = prim.numverts;
|
|
tclprim.offset = 0; /* not used */
|
|
tclprim.offset = 0; /* not used */
|
|
|
|
|
|
- radeon_cp_dispatch_vertex(dev, buf, &tclprim);
|
|
|
|
|
|
+ radeon_cp_dispatch_vertex(dev, file_priv, buf, &tclprim);
|
|
}
|
|
}
|
|
|
|
|
|
if (sarea_priv->nbox == 1)
|
|
if (sarea_priv->nbox == 1)
|
|
@@ -2560,7 +2583,7 @@ static int radeon_cp_vertex2(struct drm_device *dev, void *data, struct drm_file
|
|
}
|
|
}
|
|
|
|
|
|
if (vertex->discard) {
|
|
if (vertex->discard) {
|
|
- radeon_cp_discard_buffer(dev, buf);
|
|
|
|
|
|
+ radeon_cp_discard_buffer(dev, file_priv->master, buf);
|
|
}
|
|
}
|
|
|
|
|
|
COMMIT_RING();
|
|
COMMIT_RING();
|
|
@@ -2909,7 +2932,7 @@ static int radeon_cp_cmdbuf(struct drm_device *dev, void *data, struct drm_file
|
|
goto err;
|
|
goto err;
|
|
}
|
|
}
|
|
|
|
|
|
- radeon_cp_discard_buffer(dev, buf);
|
|
|
|
|
|
+ radeon_cp_discard_buffer(dev, file_priv->master, buf);
|
|
break;
|
|
break;
|
|
|
|
|
|
case RADEON_CMD_PACKET3:
|
|
case RADEON_CMD_PACKET3:
|
|
@@ -3020,7 +3043,7 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
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*/
|
|
*/
|
|
case RADEON_PARAM_SAREA_HANDLE:
|
|
case RADEON_PARAM_SAREA_HANDLE:
|
|
/* The lock is the first dword in the sarea. */
|
|
/* The lock is the first dword in the sarea. */
|
|
- value = (long)dev->lock.hw_lock;
|
|
|
|
|
|
+ /* no users of this parameter */
|
|
break;
|
|
break;
|
|
#endif
|
|
#endif
|
|
case RADEON_PARAM_GART_TEX_HANDLE:
|
|
case RADEON_PARAM_GART_TEX_HANDLE:
|
|
@@ -3064,6 +3087,7 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
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|
static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
|
|
static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
|
|
{
|
|
{
|
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
|
|
+ struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
|
|
drm_radeon_setparam_t *sp = data;
|
|
drm_radeon_setparam_t *sp = data;
|
|
struct drm_radeon_driver_file_fields *radeon_priv;
|
|
struct drm_radeon_driver_file_fields *radeon_priv;
|
|
|
|
|
|
@@ -3078,12 +3102,14 @@ static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_fil
|
|
DRM_DEBUG("color tiling disabled\n");
|
|
DRM_DEBUG("color tiling disabled\n");
|
|
dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO;
|
|
dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO;
|
|
dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO;
|
|
dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO;
|
|
- dev_priv->sarea_priv->tiling_enabled = 0;
|
|
|
|
|
|
+ if (master_priv->sarea_priv)
|
|
|
|
+ master_priv->sarea_priv->tiling_enabled = 0;
|
|
} else if (sp->value == 1) {
|
|
} else if (sp->value == 1) {
|
|
DRM_DEBUG("color tiling enabled\n");
|
|
DRM_DEBUG("color tiling enabled\n");
|
|
dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO;
|
|
dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO;
|
|
dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO;
|
|
dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO;
|
|
- dev_priv->sarea_priv->tiling_enabled = 1;
|
|
|
|
|
|
+ if (master_priv->sarea_priv)
|
|
|
|
+ master_priv->sarea_priv->tiling_enabled = 1;
|
|
}
|
|
}
|
|
break;
|
|
break;
|
|
case RADEON_SETPARAM_PCIGART_LOCATION:
|
|
case RADEON_SETPARAM_PCIGART_LOCATION:
|
|
@@ -3129,14 +3155,6 @@ void radeon_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
|
|
|
|
|
|
void radeon_driver_lastclose(struct drm_device *dev)
|
|
void radeon_driver_lastclose(struct drm_device *dev)
|
|
{
|
|
{
|
|
- if (dev->dev_private) {
|
|
|
|
- drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
|
|
-
|
|
|
|
- if (dev_priv->sarea_priv &&
|
|
|
|
- dev_priv->sarea_priv->pfCurrentPage != 0)
|
|
|
|
- radeon_cp_dispatch_flip(dev);
|
|
|
|
- }
|
|
|
|
-
|
|
|
|
radeon_do_release(dev);
|
|
radeon_do_release(dev);
|
|
}
|
|
}
|
|
|
|
|