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@@ -38,6 +38,7 @@ enum {
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PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
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ICH5_PMR = 0x90, /* port mapping register */
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ICH5_PCS = 0x92, /* port control and status */
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+ PIIX_SCC = 0x0A, /* sub-class code register */
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PIIX_FLAG_AHCI = (1 << 28), /* AHCI possible */
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PIIX_FLAG_CHECKINTR = (1 << 29), /* make sure PCI INTx enabled */
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@@ -62,6 +63,8 @@ enum {
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ich6_sata_rm = 4,
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ich7_sata = 5,
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esb2_sata = 6,
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+
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+ PIIX_AHCI_DEVICE = 6,
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};
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static int piix_init_one (struct pci_dev *pdev,
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@@ -574,11 +577,11 @@ static int piix_disable_ahci(struct pci_dev *pdev)
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addr = pci_resource_start(pdev, AHCI_PCI_BAR);
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if (!addr || !pci_resource_len(pdev, AHCI_PCI_BAR))
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return 0;
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-
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+
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mmio = ioremap(addr, 64);
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if (!mmio)
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return -ENOMEM;
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-
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+
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tmp = readl(mmio + AHCI_GLOBAL_CTL);
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if (tmp & AHCI_ENABLE) {
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tmp &= ~AHCI_ENABLE;
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@@ -588,7 +591,7 @@ static int piix_disable_ahci(struct pci_dev *pdev)
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if (tmp & AHCI_ENABLE)
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rc = -EIO;
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}
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-
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+
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iounmap(mmio);
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return rc;
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}
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@@ -626,9 +629,13 @@ static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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port_info[1] = NULL;
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if (port_info[0]->host_flags & PIIX_FLAG_AHCI) {
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- int rc = piix_disable_ahci(pdev);
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- if (rc)
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- return rc;
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+ u8 tmp;
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+ pci_read_config_byte(pdev, PIIX_SCC, &tmp);
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+ if (tmp == PIIX_AHCI_DEVICE) {
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+ int rc = piix_disable_ahci(pdev);
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+ if (rc)
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+ return rc;
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+ }
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}
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if (port_info[0]->host_flags & PIIX_FLAG_COMBINED) {
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