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@@ -58,6 +58,8 @@
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(((dma_is_apbh(d) && apbh_is_old(d)) ? 0x050 : 0x110) + (n) * 0x70)
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#define HW_APBHX_CHn_SEMA(d, n) \
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(((dma_is_apbh(d) && apbh_is_old(d)) ? 0x080 : 0x140) + (n) * 0x70)
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+#define HW_APBHX_CHn_BAR(d, n) \
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+ (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x070 : 0x130) + (n) * 0x70)
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/*
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* ccw bits definitions
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@@ -623,8 +625,24 @@ static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
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dma_cookie_t cookie, struct dma_tx_state *txstate)
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{
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struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
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+ struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
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+ u32 residue = 0;
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+
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+ if (mxs_chan->status == DMA_IN_PROGRESS &&
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+ mxs_chan->flags & MXS_DMA_SG_LOOP) {
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+ struct mxs_dma_ccw *last_ccw;
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+ u32 bar;
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+
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+ last_ccw = &mxs_chan->ccw[mxs_chan->desc_count - 1];
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+ residue = last_ccw->xfer_bytes + last_ccw->bufaddr;
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+
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+ bar = readl(mxs_dma->base +
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+ HW_APBHX_CHn_BAR(mxs_dma, chan->chan_id));
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+ residue -= bar;
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+ }
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- dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 0);
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+ dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
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+ residue);
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return mxs_chan->status;
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}
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