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@@ -461,7 +461,7 @@ error:
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return ret;
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}
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-static void iwl_set_pwr_vmain(struct iwl_trans *trans)
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+static void iwl_pcie_set_pwr_vmain(struct iwl_trans *trans)
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{
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/*
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* (for documentation purposes)
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@@ -483,18 +483,11 @@ static void iwl_set_pwr_vmain(struct iwl_trans *trans)
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#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
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#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
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-static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
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+static void iwl_pcie_apm_config(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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- u16 pci_lnk_ctl;
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+ u16 lctl;
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- pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL,
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- &pci_lnk_ctl);
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- return pci_lnk_ctl;
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-}
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-
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-static void iwl_apm_config(struct iwl_trans *trans)
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-{
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/*
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* HW bug W/A for instability in PCIe bus L0S->L1 transition.
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* Check if BIOS (or OS) enabled L1-ASPM on this device.
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@@ -503,7 +496,7 @@ static void iwl_apm_config(struct iwl_trans *trans)
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* If not (unlikely), enable L0S, so there is at least some
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* power savings, even without L1.
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*/
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- u16 lctl = iwl_pciexp_link_ctrl(trans);
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+ pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
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if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
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PCI_CFG_LINK_CTRL_VAL_L1_EN) {
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@@ -522,10 +515,10 @@ static void iwl_apm_config(struct iwl_trans *trans)
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/*
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* Start up NIC's basic functionality after it has been reset
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- * (e.g. after platform boot, or shutdown via iwl_apm_stop())
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+ * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
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* NOTE: This does not load uCode nor start the embedded processor
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*/
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-static int iwl_apm_init(struct iwl_trans *trans)
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+static int iwl_pcie_apm_init(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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int ret = 0;
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@@ -557,7 +550,7 @@ static int iwl_apm_init(struct iwl_trans *trans)
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iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
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- iwl_apm_config(trans);
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+ iwl_pcie_apm_config(trans);
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/* Configure analog phase-lock-loop before activating to D0A */
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if (trans->cfg->base_params->pll_cfg_val)
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@@ -603,7 +596,7 @@ out:
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return ret;
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}
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-static int iwl_apm_stop_master(struct iwl_trans *trans)
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+static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
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{
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int ret = 0;
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@@ -621,7 +614,7 @@ static int iwl_apm_stop_master(struct iwl_trans *trans)
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return ret;
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}
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-static void iwl_apm_stop(struct iwl_trans *trans)
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+static void iwl_pcie_apm_stop(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
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@@ -629,7 +622,7 @@ static void iwl_apm_stop(struct iwl_trans *trans)
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clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
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/* Stop device's DMA activity */
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- iwl_apm_stop_master(trans);
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+ iwl_pcie_apm_stop_master(trans);
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/* Reset the entire device */
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iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
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@@ -644,21 +637,21 @@ static void iwl_apm_stop(struct iwl_trans *trans)
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CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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}
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-static int iwl_nic_init(struct iwl_trans *trans)
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+static int iwl_pcie_nic_init(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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unsigned long flags;
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/* nic_init */
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spin_lock_irqsave(&trans_pcie->irq_lock, flags);
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- iwl_apm_init(trans);
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+ iwl_pcie_apm_init(trans);
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/* Set interrupt coalescing calibration timer to default (512 usecs) */
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iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
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spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
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- iwl_set_pwr_vmain(trans);
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+ iwl_pcie_set_pwr_vmain(trans);
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iwl_op_mode_nic_config(trans->op_mode);
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@@ -681,7 +674,7 @@ static int iwl_nic_init(struct iwl_trans *trans)
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#define HW_READY_TIMEOUT (50)
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/* Note: returns poll_bit return value, which is >= 0 if success */
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-static int iwl_set_hw_ready(struct iwl_trans *trans)
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+static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
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{
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int ret;
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@@ -699,14 +692,14 @@ static int iwl_set_hw_ready(struct iwl_trans *trans)
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}
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/* Note: returns standard 0/-ERROR code */
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-static int iwl_prepare_card_hw(struct iwl_trans *trans)
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+static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
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{
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int ret;
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int t = 0;
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IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
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- ret = iwl_set_hw_ready(trans);
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+ ret = iwl_pcie_set_hw_ready(trans);
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/* If the card is ready, exit 0 */
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if (ret >= 0)
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return 0;
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@@ -716,7 +709,7 @@ static int iwl_prepare_card_hw(struct iwl_trans *trans)
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CSR_HW_IF_CONFIG_REG_PREPARE);
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do {
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- ret = iwl_set_hw_ready(trans);
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+ ret = iwl_pcie_set_hw_ready(trans);
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if (ret >= 0)
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return 0;
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@@ -730,7 +723,7 @@ static int iwl_prepare_card_hw(struct iwl_trans *trans)
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/*
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* ucode
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*/
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-static int iwl_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
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+static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
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dma_addr_t phy_addr, u32 byte_cnt)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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@@ -777,7 +770,7 @@ static int iwl_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
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return 0;
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}
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-static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
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+static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
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const struct fw_desc *section)
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{
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u8 *v_addr;
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@@ -798,8 +791,9 @@ static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
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copy_size = min_t(u32, PAGE_SIZE, section->len - offset);
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memcpy(v_addr, (u8 *)section->data + offset, copy_size);
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- ret = iwl_load_firmware_chunk(trans, section->offset + offset,
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- p_addr, copy_size);
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+ ret = iwl_pcie_load_firmware_chunk(trans,
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+ section->offset + offset,
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+ p_addr, copy_size);
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if (ret) {
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IWL_ERR(trans,
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"Could not load the [%d] uCode section\n",
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@@ -812,7 +806,7 @@ static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
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return ret;
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}
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-static int iwl_load_given_ucode(struct iwl_trans *trans,
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+static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
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const struct fw_img *image)
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{
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int i, ret = 0;
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@@ -821,7 +815,7 @@ static int iwl_load_given_ucode(struct iwl_trans *trans,
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if (!image->sec[i].data)
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break;
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- ret = iwl_load_section(trans, i, &image->sec[i]);
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+ ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
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if (ret)
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return ret;
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}
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@@ -840,7 +834,7 @@ static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
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bool hw_rfkill;
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/* This may fail if AMT took ownership of the device */
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- if (iwl_prepare_card_hw(trans)) {
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+ if (iwl_pcie_prepare_card_hw(trans)) {
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IWL_WARN(trans, "Exit HW not ready\n");
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return -EIO;
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}
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@@ -857,7 +851,7 @@ static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
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iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
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- ret = iwl_nic_init(trans);
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+ ret = iwl_pcie_nic_init(trans);
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if (ret) {
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IWL_ERR(trans, "Unable to init nic\n");
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return ret;
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@@ -877,7 +871,7 @@ static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
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iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
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/* Load the given image to the HW */
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- return iwl_load_given_ucode(trans, fw);
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+ return iwl_pcie_load_given_ucode(trans, fw);
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}
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/*
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@@ -1037,7 +1031,7 @@ static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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/* Stop the device, and put it in low power state */
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- iwl_apm_stop(trans);
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+ iwl_pcie_apm_stop(trans);
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/* Upon stop, the APM issues an interrupt if HW RF kill is set.
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* Clean again the interrupt here
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@@ -1265,13 +1259,13 @@ static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
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trans_pcie->irq_requested = true;
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}
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- err = iwl_prepare_card_hw(trans);
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+ err = iwl_pcie_prepare_card_hw(trans);
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if (err) {
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IWL_ERR(trans, "Error while preparing HW: %d\n", err);
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goto err_free_irq;
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}
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- iwl_apm_init(trans);
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+ iwl_pcie_apm_init(trans);
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/* From now on, the op_mode will be kept updated about RF kill state */
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iwl_enable_rfkill_int(trans);
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@@ -1301,7 +1295,7 @@ static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
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iwl_disable_interrupts(trans);
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spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
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- iwl_apm_stop(trans);
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+ iwl_pcie_apm_stop(trans);
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spin_lock_irqsave(&trans_pcie->irq_lock, flags);
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iwl_disable_interrupts(trans);
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