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@@ -335,11 +335,11 @@ int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
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hwm = min(hwm, MAC_RXFIFO_SIZE - 8192);
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lwm = min(3 * (int)mtu, MAC_RXFIFO_SIZE / 4);
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- v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset);
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if (adap->params.rev == T3_REV_B2 &&
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(t3_read_reg(adap, A_XGM_RX_CTRL + mac->offset) & F_RXEN)) {
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disable_exact_filters(mac);
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- t3_set_reg_field(adap, A_XGM_RXFIFO_CFG + mac->offset,
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+ v = t3_read_reg(adap, A_XGM_RX_CFG + mac->offset);
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+ t3_set_reg_field(adap, A_XGM_RX_CFG + mac->offset,
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F_ENHASHMCAST | F_COPYALLFRAMES, F_DISBCAST);
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/* drain rx FIFO */
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@@ -347,11 +347,12 @@ int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
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A_XGM_RX_MAX_PKT_SIZE_ERR_CNT +
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mac->offset,
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1 << 31, 1, 20, 5)) {
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- t3_write_reg(adap, A_XGM_RXFIFO_CFG + mac->offset, v);
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+ t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
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enable_exact_filters(mac);
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return -EIO;
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}
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t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu);
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+ t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
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enable_exact_filters(mac);
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} else
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t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu);
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@@ -362,6 +363,7 @@ int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
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*/
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hwm = rx_fifo_hwm(mtu);
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lwm = min(3 * (int)mtu, MAC_RXFIFO_SIZE / 4);
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+ v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset);
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v &= ~V_RXFIFOPAUSELWM(M_RXFIFOPAUSELWM);
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v |= V_RXFIFOPAUSELWM(lwm / 8);
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if (G_RXFIFOPAUSEHWM(v))
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