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@@ -588,6 +588,9 @@ static int wl18xx_identify_chip(struct wl1271 *wl)
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WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED |
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WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN;
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+ /* PG 1.0 has some problems with MCS_13, so disable it */
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+ wl->ht_cap.mcs.rx_mask[1] &= ~BIT(5);
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+
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/* TODO: need to blocksize alignment for RX/TX separately? */
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break;
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default:
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@@ -914,6 +917,10 @@ static void wl18xx_set_rx_csum(struct wl1271 *wl,
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skb->ip_summed = CHECKSUM_UNNECESSARY;
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}
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+/*
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+ * TODO: instead of having these two functions to get the rate mask,
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+ * we should modify the wlvif->rate_set instead
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+ */
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static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl,
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struct wl12xx_vif *wlvif)
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{
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@@ -940,6 +947,17 @@ static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
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return CONF_TX_RATE_USE_WIDE_CHAN;
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} else {
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wl1271_debug(DEBUG_ACX, "using MIMO rate mask");
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+
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+ /*
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+ * PG 1.0 has some problems with MCS_13, so disable it
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+ *
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+ * TODO: instead of hacking this in here, we should
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+ * make it more general and change a bit in the
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+ * wlvif->rate_set instead.
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+ */
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+ if (wl->chip.id == CHIP_ID_185x_PG10)
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+ return CONF_TX_MIMO_RATES & ~CONF_HW_BIT_RATE_MCS_13;
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+
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return CONF_TX_MIMO_RATES;
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}
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}
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