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@@ -2238,6 +2238,32 @@ static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
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}
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}
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+static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
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+{
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+ if (dma_has_cap(DMA_SLAVE, dev->cap_mask))
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+ dev->device_prep_slave_sg = d40_prep_slave_sg;
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+
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+ if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) {
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+ dev->device_prep_dma_memcpy = d40_prep_memcpy;
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+
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+ /*
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+ * This controller can only access address at even
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+ * 32bit boundaries, i.e. 2^2
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+ */
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+ dev->copy_align = 2;
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+ }
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+
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+ if (dma_has_cap(DMA_SG, dev->cap_mask))
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+ dev->device_prep_dma_sg = d40_prep_memcpy_sg;
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+
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+ dev->device_alloc_chan_resources = d40_alloc_chan_resources;
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+ dev->device_free_chan_resources = d40_free_chan_resources;
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+ dev->device_issue_pending = d40_issue_pending;
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+ dev->device_tx_status = d40_tx_status;
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+ dev->device_control = d40_control;
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+ dev->dev = base->dev;
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+}
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+
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static int __init d40_dmaengine_init(struct d40_base *base,
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int num_reserved_chans)
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{
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@@ -2249,15 +2275,7 @@ static int __init d40_dmaengine_init(struct d40_base *base,
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dma_cap_zero(base->dma_slave.cap_mask);
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dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
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- base->dma_slave.device_alloc_chan_resources = d40_alloc_chan_resources;
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- base->dma_slave.device_free_chan_resources = d40_free_chan_resources;
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- base->dma_slave.device_prep_dma_memcpy = d40_prep_memcpy;
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- base->dma_slave.device_prep_dma_sg = d40_prep_memcpy_sg;
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- base->dma_slave.device_prep_slave_sg = d40_prep_slave_sg;
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- base->dma_slave.device_tx_status = d40_tx_status;
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- base->dma_slave.device_issue_pending = d40_issue_pending;
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- base->dma_slave.device_control = d40_control;
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- base->dma_slave.dev = base->dev;
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+ d40_ops_init(base, &base->dma_slave);
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err = dma_async_device_register(&base->dma_slave);
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@@ -2271,22 +2289,9 @@ static int __init d40_dmaengine_init(struct d40_base *base,
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dma_cap_zero(base->dma_memcpy.cap_mask);
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dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
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- dma_cap_set(DMA_SG, base->dma_slave.cap_mask);
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-
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- base->dma_memcpy.device_alloc_chan_resources = d40_alloc_chan_resources;
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- base->dma_memcpy.device_free_chan_resources = d40_free_chan_resources;
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- base->dma_memcpy.device_prep_dma_memcpy = d40_prep_memcpy;
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- base->dma_slave.device_prep_dma_sg = d40_prep_memcpy_sg;
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- base->dma_memcpy.device_prep_slave_sg = d40_prep_slave_sg;
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- base->dma_memcpy.device_tx_status = d40_tx_status;
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- base->dma_memcpy.device_issue_pending = d40_issue_pending;
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- base->dma_memcpy.device_control = d40_control;
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- base->dma_memcpy.dev = base->dev;
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- /*
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- * This controller can only access address at even
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- * 32bit boundaries, i.e. 2^2
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- */
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- base->dma_memcpy.copy_align = 2;
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+ dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask);
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+
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+ d40_ops_init(base, &base->dma_memcpy);
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err = dma_async_device_register(&base->dma_memcpy);
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@@ -2302,18 +2307,10 @@ static int __init d40_dmaengine_init(struct d40_base *base,
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dma_cap_zero(base->dma_both.cap_mask);
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dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
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dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
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- dma_cap_set(DMA_SG, base->dma_slave.cap_mask);
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-
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- base->dma_both.device_alloc_chan_resources = d40_alloc_chan_resources;
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- base->dma_both.device_free_chan_resources = d40_free_chan_resources;
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- base->dma_both.device_prep_dma_memcpy = d40_prep_memcpy;
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- base->dma_slave.device_prep_dma_sg = d40_prep_memcpy_sg;
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- base->dma_both.device_prep_slave_sg = d40_prep_slave_sg;
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- base->dma_both.device_tx_status = d40_tx_status;
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- base->dma_both.device_issue_pending = d40_issue_pending;
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- base->dma_both.device_control = d40_control;
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- base->dma_both.dev = base->dev;
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- base->dma_both.copy_align = 2;
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+ dma_cap_set(DMA_SG, base->dma_both.cap_mask);
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+
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+ d40_ops_init(base, &base->dma_both);
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+
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err = dma_async_device_register(&base->dma_both);
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if (err) {
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