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@@ -39,6 +39,8 @@ nv50_fence_context_new(struct nouveau_channel *chan)
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struct nv10_fence_chan *fctx;
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struct ttm_mem_reg *mem = &priv->bo->bo.mem;
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struct nouveau_object *object;
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+ u32 start = mem->start * PAGE_SIZE;
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+ u32 limit = start + mem->size - 1;
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int ret, i;
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fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
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@@ -51,26 +53,28 @@ nv50_fence_context_new(struct nouveau_channel *chan)
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fctx->base.sync = nv17_fence_sync;
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ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
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- NvSema, 0x0002,
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+ NvSema, 0x003d,
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&(struct nv_dma_class) {
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.flags = NV_DMA_TARGET_VRAM |
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NV_DMA_ACCESS_RDWR,
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- .start = mem->start * PAGE_SIZE,
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- .limit = mem->size - 1,
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+ .start = start,
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+ .limit = limit,
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}, sizeof(struct nv_dma_class),
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&object);
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/* dma objects for display sync channel semaphore blocks */
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for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) {
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struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
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+ u32 start = bo->bo.mem.start * PAGE_SIZE;
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+ u32 limit = start + bo->bo.mem.size - 1;
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ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
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NvEvoSema0 + i, 0x003d,
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&(struct nv_dma_class) {
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.flags = NV_DMA_TARGET_VRAM |
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NV_DMA_ACCESS_RDWR,
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- .start = bo->bo.offset,
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- .limit = bo->bo.offset + 0xfff,
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+ .start = start,
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+ .limit = limit,
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}, sizeof(struct nv_dma_class),
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&object);
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}
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