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@@ -124,7 +124,7 @@ static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
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.enabled = 1,
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};
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-static const struct event_constraint *event_constraint;
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+static const struct event_constraint *event_constraints;
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/*
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* Not sure about some of these
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@@ -1442,12 +1442,12 @@ intel_get_event_idx(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc)
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const struct event_constraint *event_constraint;
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int i, code;
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- if (!event_constraint)
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+ if (!event_constraints)
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goto skip;
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code = hwc->config & CORE_EVNTSEL_EVENT_MASK;
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- for_each_event_constraint(event_constraint, event_constraint) {
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+ for_each_event_constraint(event_constraint, event_constraints) {
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if (code == event_constraint->code) {
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for_each_bit(i, event_constraint->idxmsk, X86_PMC_IDX_MAX) {
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if (!test_and_set_bit(i, cpuc->used_mask))
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@@ -2047,12 +2047,12 @@ static int p6_pmu_init(void)
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case 7:
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case 8:
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case 11: /* Pentium III */
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- event_constraint = intel_p6_event_constraints;
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+ event_constraints = intel_p6_event_constraints;
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break;
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case 9:
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case 13:
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/* Pentium M */
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- event_constraint = intel_p6_event_constraints;
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+ event_constraints = intel_p6_event_constraints;
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break;
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default:
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pr_cont("unsupported p6 CPU model %d ",
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@@ -2124,14 +2124,14 @@ static int intel_pmu_init(void)
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sizeof(hw_cache_event_ids));
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pr_cont("Core2 events, ");
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- event_constraint = intel_core_event_constraints;
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+ event_constraints = intel_core_event_constraints;
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break;
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default:
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case 26:
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memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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- event_constraint = intel_nehalem_event_constraints;
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+ event_constraints = intel_nehalem_event_constraints;
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pr_cont("Nehalem/Corei7 events, ");
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break;
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case 28:
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