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@@ -3104,7 +3104,8 @@ static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
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void valleyview_set_rps(struct drm_device *dev, u8 val)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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- u32 limits = gen6_rps_limits(dev_priv, &val);
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+
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+ gen6_rps_limits(dev_priv, &val);
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WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
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WARN_ON(val > dev_priv->rps.max_delay);
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@@ -3123,11 +3124,6 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
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vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
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- /* Make sure we continue to get interrupts
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- * until we hit the minimum or maximum frequencies.
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- */
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- I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
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-
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dev_priv->rps.cur_delay = val;
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trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
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