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@@ -36,7 +36,6 @@
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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#include <mach/db8500-regs.h>
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-#include <mach/id.h>
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#include "dbx500-prcmu-regs.h"
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/* Offset for the firmware version within the TCPM */
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@@ -216,10 +215,8 @@
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#define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
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#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
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#define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
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-#define PRCMU_I2C_WRITE(slave) \
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- (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0))
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-#define PRCMU_I2C_READ(slave) \
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- (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0))
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+#define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
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+#define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
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#define PRCMU_I2C_STOP_EN BIT(3)
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/* Mailbox 5 ACKs */
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@@ -1049,12 +1046,13 @@ int db8500_prcmu_get_ddr_opp(void)
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*
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* This function sets the operating point of the DDR.
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*/
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+static bool enable_set_ddr_opp;
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int db8500_prcmu_set_ddr_opp(u8 opp)
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{
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if (opp < DDR_100_OPP || opp > DDR_25_OPP)
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return -EINVAL;
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/* Changing the DDR OPP can hang the hardware pre-v21 */
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- if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20())
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+ if (enable_set_ddr_opp)
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writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);
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return 0;
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@@ -2790,6 +2788,7 @@ void __init db8500_prcmu_early_init(void)
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pr_err("prcmu: Unsupported chip version\n");
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BUG();
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}
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+ tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
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spin_lock_init(&mb0_transfer.lock);
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spin_lock_init(&mb0_transfer.dbb_irqs_lock);
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@@ -3104,9 +3103,6 @@ static int db8500_prcmu_probe(struct platform_device *pdev)
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struct device_node *np = pdev->dev.of_node;
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int irq = 0, err = 0, i;
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- if (ux500_is_svp())
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- return -ENODEV;
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-
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init_prcm_registers();
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/* Clean up the mailbox interrupts after pre-kernel code. */
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@@ -3135,8 +3131,7 @@ static int db8500_prcmu_probe(struct platform_device *pdev)
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}
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}
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- if (cpu_is_u8500v20_or_later())
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- prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
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+ prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
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db8500_prcmu_update_cpufreq();
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