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@@ -3517,6 +3517,7 @@ int ni_dpm_enable(struct radeon_device *rdev)
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struct rv7xx_power_info *pi = rv770_get_pi(rdev);
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struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
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struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
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+ int ret;
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if (pi->gfx_clock_gating)
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ni_cg_clockgating_default(rdev);
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@@ -3528,10 +3529,15 @@ int ni_dpm_enable(struct radeon_device *rdev)
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ni_ls_clockgating_default(rdev);
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if (pi->voltage_control) {
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rv770_enable_voltage_control(rdev, true);
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- cypress_construct_voltage_tables(rdev);
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+ ret = cypress_construct_voltage_tables(rdev);
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+ if (ret)
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+ return ret;
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+ }
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+ if (eg_pi->dynamic_ac_timing) {
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+ ret = ni_initialize_mc_reg_table(rdev);
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+ if (ret)
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+ eg_pi->dynamic_ac_timing = false;
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}
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- if (eg_pi->dynamic_ac_timing)
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- ni_initialize_mc_reg_table(rdev);
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if (pi->dynamic_ss)
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cypress_enable_spread_spectrum(rdev, true);
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if (pi->thermal_protection)
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@@ -3545,21 +3551,43 @@ int ni_dpm_enable(struct radeon_device *rdev)
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rv770_program_vc(rdev);
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if (pi->dynamic_pcie_gen2)
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ni_enable_dynamic_pcie_gen2(rdev, true);
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- if (rv770_upload_firmware(rdev))
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- return -EINVAL;
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- ni_process_firmware_header(rdev);
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- ni_initial_switch_from_arb_f0_to_f1(rdev);
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- ni_init_smc_table(rdev);
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- ni_init_smc_spll_table(rdev);
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- ni_init_arb_table_index(rdev);
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- if (eg_pi->dynamic_ac_timing)
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- ni_populate_mc_reg_table(rdev, boot_ps);
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- ni_initialize_smc_cac_tables(rdev);
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- ni_initialize_hardware_cac_manager(rdev);
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- ni_populate_smc_tdp_limits(rdev, boot_ps);
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+ ret = rv770_upload_firmware(rdev);
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+ if (ret)
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+ return ret;
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+ ret = ni_process_firmware_header(rdev);
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+ if (ret)
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+ return ret;
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+ ret = ni_initial_switch_from_arb_f0_to_f1(rdev);
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+ if (ret)
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+ return ret;
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+ ret = ni_init_smc_table(rdev);
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+ if (ret)
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+ return ret;
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+ ret = ni_init_smc_spll_table(rdev);
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+ if (ret)
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+ return ret;
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+ ret = ni_init_arb_table_index(rdev);
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+ if (ret)
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+ return ret;
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+ if (eg_pi->dynamic_ac_timing) {
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+ ret = ni_populate_mc_reg_table(rdev, boot_ps);
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+ if (ret)
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+ return ret;
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+ }
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+ ret = ni_initialize_smc_cac_tables(rdev);
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+ if (ret)
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+ return ret;
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+ ret = ni_initialize_hardware_cac_manager(rdev);
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+ if (ret)
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+ return ret;
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+ ret = ni_populate_smc_tdp_limits(rdev, boot_ps);
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+ if (ret)
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+ return ret;
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ni_program_response_times(rdev);
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r7xx_start_smc(rdev);
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- cypress_notify_smc_display_change(rdev, false);
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+ ret = cypress_notify_smc_display_change(rdev, false);
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+ if (ret)
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+ return ret;
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cypress_enable_sclk_control(rdev, true);
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if (eg_pi->memory_transition)
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cypress_enable_mclk_control(rdev, true);
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@@ -3575,7 +3603,9 @@ int ni_dpm_enable(struct radeon_device *rdev)
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r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
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PPSMC_Result result;
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- rv770_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, 0xff * 1000);
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+ ret = rv770_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, 0xff * 1000);
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+ if (ret)
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+ return ret;
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rdev->irq.dpm_thermal = true;
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radeon_irq_set(rdev);
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result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
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@@ -3632,11 +3662,20 @@ void ni_dpm_disable(struct radeon_device *rdev)
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int ni_power_control_set_level(struct radeon_device *rdev)
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{
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struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
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+ int ret;
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- ni_restrict_performance_levels_before_switch(rdev);
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- rv770_halt_smc(rdev);
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- ni_populate_smc_tdp_limits(rdev, new_ps);
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- rv770_resume_smc(rdev);
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+ ret = ni_restrict_performance_levels_before_switch(rdev);
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+ if (ret)
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+ return ret;
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+ ret = rv770_halt_smc(rdev);
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+ if (ret)
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+ return ret;
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+ ret = ni_populate_smc_tdp_limits(rdev, new_ps);
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+ if (ret)
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+ return ret;
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+ ret = rv770_resume_smc(rdev);
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+ if (ret)
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+ return ret;
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rv770_set_sw_state(rdev);
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return 0;
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@@ -3662,29 +3701,54 @@ int ni_dpm_set_power_state(struct radeon_device *rdev)
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struct radeon_ps *old_ps = &eg_pi->current_rps;
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int ret;
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- ni_restrict_performance_levels_before_switch(rdev);
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+ ret = ni_restrict_performance_levels_before_switch(rdev);
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+ if (ret)
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+ return ret;
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rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
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- ni_enable_power_containment(rdev, new_ps, false);
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- ni_enable_smc_cac(rdev, new_ps, false);
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- rv770_halt_smc(rdev);
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+ ret = ni_enable_power_containment(rdev, new_ps, false);
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+ if (ret)
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+ return ret;
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+ ret = ni_enable_smc_cac(rdev, new_ps, false);
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+ if (ret)
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+ return ret;
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+ ret = rv770_halt_smc(rdev);
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+ if (ret)
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+ return ret;
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if (eg_pi->smu_uvd_hs)
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btc_notify_uvd_to_smc(rdev, new_ps);
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- ni_upload_sw_state(rdev, new_ps);
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- if (eg_pi->dynamic_ac_timing)
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- ni_upload_mc_reg_table(rdev, new_ps);
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+ ret = ni_upload_sw_state(rdev, new_ps);
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+ if (ret)
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+ return ret;
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+ if (eg_pi->dynamic_ac_timing) {
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+ ret = ni_upload_mc_reg_table(rdev, new_ps);
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+ if (ret)
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+ return ret;
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+ }
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ret = ni_program_memory_timing_parameters(rdev, new_ps);
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if (ret)
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return ret;
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- ni_populate_smc_tdp_limits(rdev, new_ps);
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- rv770_resume_smc(rdev);
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- rv770_set_sw_state(rdev);
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+ ret = ni_populate_smc_tdp_limits(rdev, new_ps);
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+ if (ret)
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+ return ret;
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+ ret = rv770_resume_smc(rdev);
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+ if (ret)
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+ return ret;
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+ ret = rv770_set_sw_state(rdev);
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+ if (ret)
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+ return ret;
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rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
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- ni_enable_smc_cac(rdev, new_ps, true);
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- ni_enable_power_containment(rdev, new_ps, true);
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+ ret = ni_enable_smc_cac(rdev, new_ps, true);
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+ if (ret)
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+ return ret;
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+ ret = ni_enable_power_containment(rdev, new_ps, true);
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+ if (ret)
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+ return ret;
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#if 0
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/* XXX */
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- ni_unrestrict_performance_levels_after_switch(rdev);
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+ ret = ni_unrestrict_performance_levels_after_switch(rdev);
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+ if (ret)
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+ return ret;
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#endif
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return 0;
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