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@@ -17,6 +17,7 @@
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/* Somebody depends on this; sigh... */
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#include <linux/mm.h>
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+#include <linux/io.h>
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/* Look at Documentation/cachetlb.txt */
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@@ -60,7 +61,6 @@ void microblaze_cache_init(void);
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#define invalidate_icache() mbc->iin();
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#define invalidate_icache_range(start, end) mbc->iinr(start, end);
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-
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#define flush_icache_user_range(vma, pg, adr, len) flush_icache();
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#define flush_icache_page(vma, pg) do { } while (0)
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@@ -72,9 +72,15 @@ void microblaze_cache_init(void);
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#define flush_dcache() mbc->dfl();
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#define flush_dcache_range(start, end) mbc->dflr(start, end);
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-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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-/* D-cache aliasing problem can't happen - cache is between MMU and ram */
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-#define flush_dcache_page(page) do { } while (0)
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+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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+/* MS: We have to implement it because of rootfs-jffs2 issue on WB */
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+#define flush_dcache_page(page) \
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+do { \
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+ unsigned long addr = (unsigned long) page_address(page); /* virtual */ \
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+ addr = (u32)virt_to_phys((void *)addr); \
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+ flush_dcache_range((unsigned) (addr), (unsigned) (addr) + PAGE_SIZE); \
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+} while (0);
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+
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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