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@@ -281,7 +281,8 @@ static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
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/* Memory controller */
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/* Memory controller */
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{ PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
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{ PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
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{ PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
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{ PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
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- /* Exists only for RDIMM */
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+
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+ /* Exists only for RDIMM */
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{ PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1 },
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{ PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1 },
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{ PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
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{ PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
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@@ -302,16 +303,6 @@ static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
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{ PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
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{ PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
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{ PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
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{ PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
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{ PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
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{ PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
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-
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- /* Generic Non-core registers */
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- /*
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- * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
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- * On Xeon 55xx, however, it has a different id (8086:2c40). So,
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- * the probing code needs to test for the other address in case of
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- * failure of this one
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- */
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- { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE) },
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-
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};
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};
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static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
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static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
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@@ -328,12 +319,6 @@ static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
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{ PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
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{ PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
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{ PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
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{ PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
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{ PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC) },
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{ PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC) },
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-
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- /*
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- * This is the PCI device has an alternate address on some
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- * processors like Core i7 860
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- */
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- { PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE) },
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};
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};
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static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
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static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
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@@ -361,10 +346,6 @@ static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
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{ PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
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{ PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
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{ PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
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{ PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
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{ PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) },
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{ PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) },
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-
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- /* Generic Non-core registers */
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- { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2) },
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-
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};
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};
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#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
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#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
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@@ -1342,20 +1323,6 @@ static int i7core_get_onedevice(struct pci_dev **prev,
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pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
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pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
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dev_descr->dev_id, *prev);
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dev_descr->dev_id, *prev);
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- /*
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- * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
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- * is at addr 8086:2c40, instead of 8086:2c41. So, we need
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- * to probe for the alternate address in case of failure
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- */
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- if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev)
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- pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
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- PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev);
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-
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- if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && !pdev)
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- pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
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- PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT,
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- *prev);
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-
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if (!pdev) {
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if (!pdev) {
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if (*prev) {
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if (*prev) {
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*prev = pdev;
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*prev = pdev;
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