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@@ -793,10 +793,14 @@ EXPORT_SYMBOL(ath9k_hw_disable_interrupts);
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void ath9k_hw_enable_interrupts(struct ath_hw *ah)
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void ath9k_hw_enable_interrupts(struct ath_hw *ah)
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{
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{
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath_common *common = ath9k_hw_common(ah);
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+ u32 sync_default = AR_INTR_SYNC_DEFAULT;
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if (!(ah->imask & ATH9K_INT_GLOBAL))
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if (!(ah->imask & ATH9K_INT_GLOBAL))
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return;
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return;
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+ if (AR_SREV_9340(ah))
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+ sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
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+
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ath_dbg(common, ATH_DBG_INTERRUPT, "enable IER\n");
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ath_dbg(common, ATH_DBG_INTERRUPT, "enable IER\n");
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REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
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REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
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if (!AR_SREV_9100(ah)) {
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if (!AR_SREV_9100(ah)) {
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@@ -805,10 +809,8 @@ void ath9k_hw_enable_interrupts(struct ath_hw *ah)
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REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
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REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
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- REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
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- AR_INTR_SYNC_DEFAULT);
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- REG_WRITE(ah, AR_INTR_SYNC_MASK,
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- AR_INTR_SYNC_DEFAULT);
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+ REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
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+ REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default);
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}
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}
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ath_dbg(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
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ath_dbg(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
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REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
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REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
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