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@@ -155,12 +155,14 @@ static unsigned char gpio_int_unmasked[3];
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static unsigned char gpio_int_enabled[3];
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static unsigned char gpio_int_type1[3];
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static unsigned char gpio_int_type2[3];
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+static unsigned char gpio_int_debouce[3];
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/* Port ordering is: A B F */
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static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
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static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
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static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
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static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
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+static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
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void ep93xx_gpio_update_int_params(unsigned port)
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{
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@@ -183,6 +185,22 @@ void ep93xx_gpio_int_mask(unsigned line)
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gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
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}
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+void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
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+{
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+ int line = irq_to_gpio(irq);
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+ int port = line >> 3;
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+ int port_mask = 1 << (line & 7);
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+
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+ if (enable)
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+ gpio_int_debouce[port] |= port_mask;
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+ else
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+ gpio_int_debouce[port] &= ~port_mask;
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+
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+ __raw_writeb(gpio_int_debouce[port],
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+ EP93XX_GPIO_REG(int_debounce_register_offset[port]));
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+}
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+EXPORT_SYMBOL(ep93xx_gpio_int_debounce);
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+
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/*************************************************************************
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* EP93xx IRQ handling
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*************************************************************************/
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