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@@ -526,6 +526,186 @@ static struct ab8500_regulator_info
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};
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+struct ab8500_reg_init {
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+ u8 bank;
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+ u8 addr;
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+ u8 mask;
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+};
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+
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+#define REG_INIT(_id, _bank, _addr, _mask) \
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+ [_id] = { \
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+ .bank = _bank, \
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+ .addr = _addr, \
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+ .mask = _mask, \
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+ }
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+
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+static struct ab8500_reg_init ab8500_reg_init[] = {
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+ /*
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+ * 0x30, VanaRequestCtrl
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+ * 0x0C, VpllRequestCtrl
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+ * 0xc0, VextSupply1RequestCtrl
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+ */
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+ REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xfc),
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+ /*
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+ * 0x03, VextSupply2RequestCtrl
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+ * 0x0c, VextSupply3RequestCtrl
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+ * 0x30, Vaux1RequestCtrl
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+ * 0xc0, Vaux2RequestCtrl
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+ */
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+ REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
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+ /*
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+ * 0x03, Vaux3RequestCtrl
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+ * 0x04, SwHPReq
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+ */
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+ REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
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+ /*
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+ * 0x08, VanaSysClkReq1HPValid
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+ * 0x20, Vaux1SysClkReq1HPValid
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+ * 0x40, Vaux2SysClkReq1HPValid
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+ * 0x80, Vaux3SysClkReq1HPValid
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+ */
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+ REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8),
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+ /*
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+ * 0x10, VextSupply1SysClkReq1HPValid
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+ * 0x20, VextSupply2SysClkReq1HPValid
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+ * 0x40, VextSupply3SysClkReq1HPValid
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+ */
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+ REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70),
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+ /*
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+ * 0x08, VanaHwHPReq1Valid
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+ * 0x20, Vaux1HwHPReq1Valid
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+ * 0x40, Vaux2HwHPReq1Valid
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+ * 0x80, Vaux3HwHPReq1Valid
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+ */
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+ REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8),
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+ /*
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+ * 0x01, VextSupply1HwHPReq1Valid
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+ * 0x02, VextSupply2HwHPReq1Valid
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+ * 0x04, VextSupply3HwHPReq1Valid
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+ */
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+ REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
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+ /*
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+ * 0x08, VanaHwHPReq2Valid
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+ * 0x20, Vaux1HwHPReq2Valid
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+ * 0x40, Vaux2HwHPReq2Valid
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+ * 0x80, Vaux3HwHPReq2Valid
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+ */
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+ REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8),
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+ /*
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+ * 0x01, VextSupply1HwHPReq2Valid
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+ * 0x02, VextSupply2HwHPReq2Valid
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+ * 0x04, VextSupply3HwHPReq2Valid
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+ */
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+ REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
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+ /*
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+ * 0x20, VanaSwHPReqValid
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+ * 0x80, Vaux1SwHPReqValid
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+ */
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+ REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0),
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+ /*
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+ * 0x01, Vaux2SwHPReqValid
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+ * 0x02, Vaux3SwHPReqValid
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+ * 0x04, VextSupply1SwHPReqValid
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+ * 0x08, VextSupply2SwHPReqValid
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+ * 0x10, VextSupply3SwHPReqValid
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+ */
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+ REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
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+ /*
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+ * 0x02, SysClkReq2Valid1
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+ * ...
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+ * 0x80, SysClkReq8Valid1
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+ */
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+ REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
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+ /*
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+ * 0x02, SysClkReq2Valid2
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+ * ...
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+ * 0x80, SysClkReq8Valid2
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+ */
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+ REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
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+ /*
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+ * 0x02, VTVoutEna
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+ * 0x04, Vintcore12Ena
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+ * 0x38, Vintcore12Sel
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+ * 0x40, Vintcore12LP
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+ * 0x80, VTVoutLP
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+ */
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+ REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe),
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+ /*
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+ * 0x02, VaudioEna
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+ * 0x04, VdmicEna
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+ * 0x08, Vamic1Ena
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+ * 0x10, Vamic2Ena
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+ */
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+ REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
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+ /*
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+ * 0x01, Vamic1_dzout
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+ * 0x02, Vamic2_dzout
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+ */
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+ REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
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+ /*
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+ * 0x0c, VanaRegu
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+ * 0x03, VpllRegu
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+ */
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+ REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f),
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+ /*
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+ * 0x01, VrefDDREna
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+ * 0x02, VrefDDRSleepMode
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+ */
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+ REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03),
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+ /*
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+ * 0x03, VextSupply1Regu
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+ * 0x0c, VextSupply2Regu
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+ * 0x30, VextSupply3Regu
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+ * 0x40, ExtSupply2Bypass
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+ * 0x80, ExtSupply3Bypass
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+ */
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+ REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
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+ /*
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+ * 0x03, Vaux1Regu
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+ * 0x0c, Vaux2Regu
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+ */
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+ REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f),
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+ /*
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+ * 0x03, Vaux3Regu
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+ */
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+ REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03),
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+ /*
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+ * 0x3f, Vsmps1Sel1
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+ */
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+ REG_INIT(AB8500_VSMPS1SEL1, 0x04, 0x13, 0x3f),
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+ /*
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+ * 0x0f, Vaux1Sel
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+ */
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+ REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f),
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+ /*
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+ * 0x0f, Vaux2Sel
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+ */
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+ REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f),
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+ /*
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+ * 0x07, Vaux3Sel
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+ */
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+ REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07),
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+ /*
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+ * 0x01, VextSupply12LP
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+ */
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+ REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
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+ /*
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+ * 0x04, Vaux1Disch
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+ * 0x08, Vaux2Disch
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+ * 0x10, Vaux3Disch
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+ * 0x20, Vintcore12Disch
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+ * 0x40, VTVoutDisch
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+ * 0x80, VaudioDisch
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+ */
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+ REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
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+ /*
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+ * 0x02, VanaDisch
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+ * 0x04, VdmicPullDownEna
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+ * 0x10, VdmicDisch
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+ */
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+ REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
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+};
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+
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static __devinit int ab8500_regulator_probe(struct platform_device *pdev)
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{
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struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
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@@ -544,10 +724,51 @@ static __devinit int ab8500_regulator_probe(struct platform_device *pdev)
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/* make sure the platform data has the correct size */
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if (pdata->num_regulator != ARRAY_SIZE(ab8500_regulator_info)) {
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- dev_err(&pdev->dev, "platform configuration error\n");
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+ dev_err(&pdev->dev, "Configuration error: size mismatch.\n");
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return -EINVAL;
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}
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+ /* initialize registers */
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+ for (i = 0; i < pdata->num_regulator_reg_init; i++) {
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+ int id;
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+ u8 value;
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+
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+ id = pdata->regulator_reg_init[i].id;
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+ value = pdata->regulator_reg_init[i].value;
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+
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+ /* check for configuration errors */
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+ if (id >= AB8500_NUM_REGULATOR_REGISTERS) {
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+ dev_err(&pdev->dev,
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+ "Configuration error: id outside range.\n");
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+ return -EINVAL;
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+ }
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+ if (value & ~ab8500_reg_init[id].mask) {
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+ dev_err(&pdev->dev,
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+ "Configuration error: value outside mask.\n");
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+ return -EINVAL;
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+ }
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+
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+ /* initialize register */
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+ err = abx500_mask_and_set_register_interruptible(&pdev->dev,
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+ ab8500_reg_init[id].bank,
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+ ab8500_reg_init[id].addr,
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+ ab8500_reg_init[id].mask,
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+ value);
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+ if (err < 0) {
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+ dev_err(&pdev->dev,
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+ "Failed to initialize 0x%02x, 0x%02x.\n",
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+ ab8500_reg_init[id].bank,
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+ ab8500_reg_init[id].addr);
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+ return err;
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+ }
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+ dev_vdbg(&pdev->dev,
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+ " init: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
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+ ab8500_reg_init[id].bank,
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+ ab8500_reg_init[id].addr,
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+ ab8500_reg_init[id].mask,
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+ value);
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+ }
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+
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/* register all regulators */
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for (i = 0; i < ARRAY_SIZE(ab8500_regulator_info); i++) {
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struct ab8500_regulator_info *info = NULL;
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