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@@ -211,7 +211,7 @@ void omap2_init_dpll_parent(struct clk *clk)
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if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
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v == OMAP3XXX_EN_DPLL_FRBYPASS)
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clk_reparent(clk, dd->clk_bypass);
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- } else if (cpu_is_omap44xx()) {
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+ } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
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if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
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v == OMAP4XXX_EN_DPLL_FRBYPASS ||
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v == OMAP4XXX_EN_DPLL_MNBYPASS)
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@@ -257,7 +257,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
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if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
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v == OMAP3XXX_EN_DPLL_FRBYPASS)
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return dd->clk_bypass->rate;
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- } else if (cpu_is_omap44xx()) {
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+ } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
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if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
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v == OMAP4XXX_EN_DPLL_FRBYPASS ||
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v == OMAP4XXX_EN_DPLL_MNBYPASS)
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