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@@ -0,0 +1,376 @@
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+/*
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+ * OHCI HCD(Host Controller Driver) for USB.
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+ *
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+ *(C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
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+ *(C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
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+ *(C) Copyright 2002 Hewlett-Packard Company
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+ *
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+ * Bus glue for Toshiba Mobile IO(TMIO) Controller's OHCI core
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+ * (C) Copyright 2005 Chris Humbert <mahadri-usb@drigon.com>
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+ * (C) Copyright 2007, 2008 Dmitry Baryshkov <dbaryshkov@gmail.com>
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+ *
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+ * This is known to work with the following variants:
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+ * TC6393XB revision 3 (32kB SRAM)
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+ *
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+ * The TMIO's OHCI core DMAs through a small internal buffer that
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+ * is directly addressable by the CPU.
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+ *
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+ * Written from sparse documentation from Toshiba and Sharp's driver
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+ * for the 2.4 kernel,
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+ * usb-ohci-tc6393.c(C) Copyright 2004 Lineo Solutions, Inc.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+/*#include <linux/fs.h>
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+#include <linux/mount.h>
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+#include <linux/pagemap.h>
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+#include <linux/init.h>
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+#include <linux/namei.h>
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+#include <linux/sched.h>*/
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+#include <linux/platform_device.h>
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+#include <linux/mfd/core.h>
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+#include <linux/mfd/tmio.h>
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+#include <linux/dma-mapping.h>
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+
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+/*-------------------------------------------------------------------------*/
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+
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+/*
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+ * USB Host Controller Configuration Register
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+ */
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+#define CCR_REVID 0x08 /* b Revision ID */
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+#define CCR_BASE 0x10 /* l USB Control Register Base Address Low */
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+#define CCR_ILME 0x40 /* b Internal Local Memory Enable */
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+#define CCR_PM 0x4c /* w Power Management */
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+#define CCR_INTC 0x50 /* b INT Control */
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+#define CCR_LMW1L 0x54 /* w Local Memory Window 1 LMADRS Low */
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+#define CCR_LMW1H 0x56 /* w Local Memory Window 1 LMADRS High */
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+#define CCR_LMW1BL 0x58 /* w Local Memory Window 1 Base Address Low */
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+#define CCR_LMW1BH 0x5A /* w Local Memory Window 1 Base Address High */
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+#define CCR_LMW2L 0x5C /* w Local Memory Window 2 LMADRS Low */
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+#define CCR_LMW2H 0x5E /* w Local Memory Window 2 LMADRS High */
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+#define CCR_LMW2BL 0x60 /* w Local Memory Window 2 Base Address Low */
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+#define CCR_LMW2BH 0x62 /* w Local Memory Window 2 Base Address High */
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+#define CCR_MISC 0xFC /* b MISC */
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+
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+#define CCR_PM_GKEN 0x0001
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+#define CCR_PM_CKRNEN 0x0002
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+#define CCR_PM_USBPW1 0x0004
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+#define CCR_PM_USBPW2 0x0008
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+#define CCR_PM_USBPW3 0x0008
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+#define CCR_PM_PMEE 0x0100
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+#define CCR_PM_PMES 0x8000
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+
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+/*-------------------------------------------------------------------------*/
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+
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+struct tmio_hcd {
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+ void __iomem *ccr;
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+ spinlock_t lock; /* protects RMW cycles */
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+};
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+
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+#define hcd_to_tmio(hcd) ((struct tmio_hcd *)(hcd_to_ohci(hcd) + 1))
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+
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+/*-------------------------------------------------------------------------*/
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+
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+static void tmio_write_pm(struct platform_device *dev)
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+{
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+ struct usb_hcd *hcd = platform_get_drvdata(dev);
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+ struct tmio_hcd *tmio = hcd_to_tmio(hcd);
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+ u16 pm;
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&tmio->lock, flags);
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+
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+ pm = CCR_PM_GKEN | CCR_PM_CKRNEN |
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+ CCR_PM_PMEE | CCR_PM_PMES;
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+
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+ tmio_iowrite16(pm, tmio->ccr + CCR_PM);
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+ spin_unlock_irqrestore(&tmio->lock, flags);
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+}
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+
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+static void tmio_stop_hc(struct platform_device *dev)
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+{
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+ struct usb_hcd *hcd = platform_get_drvdata(dev);
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+ struct ohci_hcd *ohci = hcd_to_ohci(hcd);
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+ struct tmio_hcd *tmio = hcd_to_tmio(hcd);
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+ u16 pm;
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+
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+ pm = CCR_PM_GKEN | CCR_PM_CKRNEN;
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+ switch (ohci->num_ports) {
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+ default:
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+ dev_err(&dev->dev, "Unsupported amount of ports: %d\n", ohci->num_ports);
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+ case 3:
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+ pm |= CCR_PM_USBPW3;
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+ case 2:
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+ pm |= CCR_PM_USBPW2;
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+ case 1:
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+ pm |= CCR_PM_USBPW1;
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+ }
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+ tmio_iowrite8(0, tmio->ccr + CCR_INTC);
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+ tmio_iowrite8(0, tmio->ccr + CCR_ILME);
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+ tmio_iowrite16(0, tmio->ccr + CCR_BASE);
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+ tmio_iowrite16(0, tmio->ccr + CCR_BASE + 2);
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+ tmio_iowrite16(pm, tmio->ccr + CCR_PM);
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+}
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+
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+static void tmio_start_hc(struct platform_device *dev)
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+{
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+ struct usb_hcd *hcd = platform_get_drvdata(dev);
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+ struct tmio_hcd *tmio = hcd_to_tmio(hcd);
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+ unsigned long base = hcd->rsrc_start;
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+
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+ tmio_write_pm(dev);
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+ tmio_iowrite16(base, tmio->ccr + CCR_BASE);
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+ tmio_iowrite16(base >> 16, tmio->ccr + CCR_BASE + 2);
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+ tmio_iowrite8(1, tmio->ccr + CCR_ILME);
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+ tmio_iowrite8(2, tmio->ccr + CCR_INTC);
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+
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+ dev_info(&dev->dev, "revision %d @ 0x%08llx, irq %d\n",
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+ tmio_ioread8(tmio->ccr + CCR_REVID), hcd->rsrc_start, hcd->irq);
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+}
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+
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+static int ohci_tmio_start(struct usb_hcd *hcd)
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+{
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+ struct ohci_hcd *ohci = hcd_to_ohci(hcd);
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+ int ret;
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+
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+ if ((ret = ohci_init(ohci)) < 0)
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+ return ret;
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+
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+ if ((ret = ohci_run(ohci)) < 0) {
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+ err("can't start %s", hcd->self.bus_name);
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+ ohci_stop(hcd);
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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+static const struct hc_driver ohci_tmio_hc_driver = {
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+ .description = hcd_name,
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+ .product_desc = "TMIO OHCI USB Host Controller",
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+ .hcd_priv_size = sizeof(struct ohci_hcd) + sizeof (struct tmio_hcd),
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+
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+ /* generic hardware linkage */
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+ .irq = ohci_irq,
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+ .flags = HCD_USB11 | HCD_MEMORY | HCD_LOCAL_MEM,
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+
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+ /* basic lifecycle operations */
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+ .start = ohci_tmio_start,
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+ .stop = ohci_stop,
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+ .shutdown = ohci_shutdown,
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+
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+ /* managing i/o requests and associated device resources */
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+ .urb_enqueue = ohci_urb_enqueue,
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+ .urb_dequeue = ohci_urb_dequeue,
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+ .endpoint_disable = ohci_endpoint_disable,
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+
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+ /* scheduling support */
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+ .get_frame_number = ohci_get_frame,
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+
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+ /* root hub support */
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+ .hub_status_data = ohci_hub_status_data,
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+ .hub_control = ohci_hub_control,
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+#ifdef CONFIG_PM
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+ .bus_suspend = ohci_bus_suspend,
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+ .bus_resume = ohci_bus_resume,
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+#endif
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+ .start_port_reset = ohci_start_port_reset,
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+};
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+
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+/*-------------------------------------------------------------------------*/
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+static struct platform_driver ohci_hcd_tmio_driver;
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+
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+static int __devinit ohci_hcd_tmio_drv_probe(struct platform_device *dev)
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+{
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+ struct mfd_cell *cell = dev->dev.platform_data;
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+ struct resource *regs = platform_get_resource(dev, IORESOURCE_MEM, 0);
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+ struct resource *config = platform_get_resource(dev, IORESOURCE_MEM, 1);
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+ struct resource *sram = platform_get_resource(dev, IORESOURCE_MEM, 2);
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+ int irq = platform_get_irq(dev, 0);
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+ struct tmio_hcd *tmio;
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+ struct ohci_hcd *ohci;
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+ struct usb_hcd *hcd;
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+ int ret;
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+
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+ if (usb_disabled())
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+ return -ENODEV;
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+
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+ if (!cell)
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+ return -EINVAL;
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+
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+ hcd = usb_create_hcd(&ohci_tmio_hc_driver, &dev->dev, dev->dev.bus_id);
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+ if (!hcd) {
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+ ret = -ENOMEM;
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+ goto err_usb_create_hcd;
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+ }
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+
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+ hcd->rsrc_start = regs->start;
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+ hcd->rsrc_len = regs->end - regs->start + 1;
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+
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+ tmio = hcd_to_tmio(hcd);
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+
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+ spin_lock_init(&tmio->lock);
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+
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+ tmio->ccr = ioremap(config->start, config->end - config->start + 1);
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+ if (!tmio->ccr) {
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+ ret = -ENOMEM;
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+ goto err_ioremap_ccr;
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+ }
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+
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+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
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+ if (!hcd->regs) {
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+ ret = -ENOMEM;
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+ goto err_ioremap_regs;
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+ }
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+
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+ if (!dma_declare_coherent_memory(&dev->dev, sram->start,
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+ sram->start,
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+ sram->end - sram->start + 1,
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+ DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE)) {
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+ ret = -EBUSY;
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+ goto err_dma_declare;
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+ }
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+
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+ if (cell->enable) {
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+ ret = cell->enable(dev);
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+ if (ret)
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+ goto err_enable;
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+ }
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+
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+ tmio_start_hc(dev);
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+ ohci = hcd_to_ohci(hcd);
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+ ohci_hcd_init(ohci);
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+
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+ ret = usb_add_hcd(hcd, irq, IRQF_DISABLED);
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+ if (ret)
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+ goto err_add_hcd;
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+
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+ if (ret == 0)
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+ return ret;
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+
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+ usb_remove_hcd(hcd);
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+
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+err_add_hcd:
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+ tmio_stop_hc(dev);
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+ if (cell->disable)
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+ cell->disable(dev);
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+err_enable:
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+ dma_release_declared_memory(&dev->dev);
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+err_dma_declare:
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+ iounmap(hcd->regs);
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+err_ioremap_regs:
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+ iounmap(tmio->ccr);
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+err_ioremap_ccr:
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+ usb_put_hcd(hcd);
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+err_usb_create_hcd:
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+
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+ return ret;
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+}
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+
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+static int __devexit ohci_hcd_tmio_drv_remove(struct platform_device *dev)
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+{
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+ struct usb_hcd *hcd = platform_get_drvdata(dev);
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+ struct tmio_hcd *tmio = hcd_to_tmio(hcd);
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+ struct mfd_cell *cell = dev->dev.platform_data;
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+
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+ usb_remove_hcd(hcd);
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+ tmio_stop_hc(dev);
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+ if (cell->disable)
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+ cell->disable(dev);
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+ dma_release_declared_memory(&dev->dev);
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+ iounmap(hcd->regs);
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+ iounmap(tmio->ccr);
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+ usb_put_hcd(hcd);
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+
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+ platform_set_drvdata(dev, NULL);
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+
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+ return 0;
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+}
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+
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+#ifdef CONFIG_PM
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+static int ohci_hcd_tmio_drv_suspend(struct platform_device *dev, pm_message_t state)
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+{
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+ struct mfd_cell *cell = dev->dev.platform_data;
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+ struct usb_hcd *hcd = platform_get_drvdata(dev);
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+ struct ohci_hcd *ohci = hcd_to_ohci(hcd);
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+ struct tmio_hcd *tmio = hcd_to_tmio(hcd);
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+ unsigned long flags;
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+ u8 misc;
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+ int ret;
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+
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+ if (time_before(jiffies, ohci->next_statechange))
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+ msleep(5);
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+ ohci->next_statechange = jiffies;
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+
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+ spin_lock_irqsave(&tmio->lock, flags);
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+
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+ misc = tmio_ioread8(tmio->ccr + CCR_MISC);
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+ misc |= 1 << 3; /* USSUSP */
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+ tmio_iowrite8(misc, tmio->ccr + CCR_MISC);
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+
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+ spin_unlock_irqrestore(&tmio->lock, flags);
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+
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+ if (cell->suspend) {
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+ ret = cell->suspend(dev);
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+ if (ret)
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+ return ret;
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+ }
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+
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+ hcd->state = HC_STATE_SUSPENDED;
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+
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+ return 0;
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+}
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+
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+static int ohci_hcd_tmio_drv_resume(struct platform_device *dev)
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+{
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+ struct mfd_cell *cell = dev->dev.platform_data;
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+ struct usb_hcd *hcd = platform_get_drvdata(dev);
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+ struct ohci_hcd *ohci = hcd_to_ohci(hcd);
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+ struct tmio_hcd *tmio = hcd_to_tmio(hcd);
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+ unsigned long flags;
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+ u8 misc;
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+ int ret;
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+
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+ if (time_before(jiffies, ohci->next_statechange))
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+ msleep(5);
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+ ohci->next_statechange = jiffies;
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+
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+ if (cell->resume) {
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+ ret = cell->resume(dev);
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+ if (ret)
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+ return ret;
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+ }
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+
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+ tmio_start_hc(dev);
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+
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+ spin_lock_irqsave(&tmio->lock, flags);
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+
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+ misc = tmio_ioread8(tmio->ccr + CCR_MISC);
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+ misc &= ~(1 << 3); /* USSUSP */
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+ tmio_iowrite8(misc, tmio->ccr + CCR_MISC);
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+
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+ spin_unlock_irqrestore(&tmio->lock, flags);
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+
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+ ohci_finish_controller_resume(hcd);
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+
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+ return 0;
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+}
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+#else
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+#define ohci_hcd_tmio_drv_suspend NULL
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+#define ohci_hcd_tmio_drv_resume NULL
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+#endif
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+
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+static struct platform_driver ohci_hcd_tmio_driver = {
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+ .probe = ohci_hcd_tmio_drv_probe,
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+ .remove = __devexit_p(ohci_hcd_tmio_drv_remove),
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+ .shutdown = usb_hcd_platform_shutdown,
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+ .suspend = ohci_hcd_tmio_drv_suspend,
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+ .resume = ohci_hcd_tmio_drv_resume,
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+ .driver = {
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+ .name = "tmio-ohci",
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+ .owner = THIS_MODULE,
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+ },
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+};
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