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@@ -0,0 +1,586 @@
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+/*
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+ * 8253/8254 interval timer emulation
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+ *
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+ * Copyright (c) 2003-2004 Fabrice Bellard
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+ * Copyright (c) 2006 Intel Corporation
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+ * Copyright (c) 2007 Keir Fraser, XenSource Inc
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+ * Copyright (c) 2008 Intel Corporation
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a copy
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+ * of this software and associated documentation files (the "Software"), to deal
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+ * in the Software without restriction, including without limitation the rights
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+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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+ * copies of the Software, and to permit persons to whom the Software is
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+ * furnished to do so, subject to the following conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be included in
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+ * all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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+ * THE SOFTWARE.
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+ *
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+ * Authors:
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+ * Sheng Yang <sheng.yang@intel.com>
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+ * Based on QEMU and Xen.
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+ */
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+
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+#include <linux/kvm_host.h>
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+
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+#include "irq.h"
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+#include "i8254.h"
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+
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+#ifndef CONFIG_X86_64
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+#define mod_64(x, y) ((x) - (y) * div64_64(x, y))
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+#else
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+#define mod_64(x, y) ((x) % (y))
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+#endif
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+
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+#define RW_STATE_LSB 1
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+#define RW_STATE_MSB 2
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+#define RW_STATE_WORD0 3
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+#define RW_STATE_WORD1 4
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+
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+/* Compute with 96 bit intermediate result: (a*b)/c */
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+static u64 muldiv64(u64 a, u32 b, u32 c)
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+{
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+ union {
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+ u64 ll;
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+ struct {
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+ u32 low, high;
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+ } l;
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+ } u, res;
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+ u64 rl, rh;
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+
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+ u.ll = a;
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+ rl = (u64)u.l.low * (u64)b;
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+ rh = (u64)u.l.high * (u64)b;
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+ rh += (rl >> 32);
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+ res.l.high = div64_64(rh, c);
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+ res.l.low = div64_64(((mod_64(rh, c) << 32) + (rl & 0xffffffff)), c);
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+ return res.ll;
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+}
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+
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+static void pit_set_gate(struct kvm *kvm, int channel, u32 val)
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+{
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+ struct kvm_kpit_channel_state *c =
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+ &kvm->arch.vpit->pit_state.channels[channel];
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+
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+ WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
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+
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+ switch (c->mode) {
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+ default:
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+ case 0:
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+ case 4:
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+ /* XXX: just disable/enable counting */
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+ break;
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+ case 1:
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+ case 2:
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+ case 3:
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+ case 5:
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+ /* Restart counting on rising edge. */
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+ if (c->gate < val)
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+ c->count_load_time = ktime_get();
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+ break;
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+ }
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+
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+ c->gate = val;
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+}
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+
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+int pit_get_gate(struct kvm *kvm, int channel)
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+{
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+ WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
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+
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+ return kvm->arch.vpit->pit_state.channels[channel].gate;
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+}
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+
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+static int pit_get_count(struct kvm *kvm, int channel)
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+{
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+ struct kvm_kpit_channel_state *c =
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+ &kvm->arch.vpit->pit_state.channels[channel];
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+ s64 d, t;
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+ int counter;
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+
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+ WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
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+
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+ t = ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
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+ d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);
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+
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+ switch (c->mode) {
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+ case 0:
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+ case 1:
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+ case 4:
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+ case 5:
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+ counter = (c->count - d) & 0xffff;
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+ break;
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+ case 3:
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+ /* XXX: may be incorrect for odd counts */
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+ counter = c->count - (mod_64((2 * d), c->count));
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+ break;
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+ default:
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+ counter = c->count - mod_64(d, c->count);
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+ break;
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+ }
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+ return counter;
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+}
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+
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+static int pit_get_out(struct kvm *kvm, int channel)
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+{
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+ struct kvm_kpit_channel_state *c =
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+ &kvm->arch.vpit->pit_state.channels[channel];
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+ s64 d, t;
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+ int out;
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+
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+ WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
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+
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+ t = ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time));
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+ d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC);
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+
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+ switch (c->mode) {
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+ default:
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+ case 0:
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+ out = (d >= c->count);
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+ break;
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+ case 1:
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+ out = (d < c->count);
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+ break;
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+ case 2:
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+ out = ((mod_64(d, c->count) == 0) && (d != 0));
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+ break;
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+ case 3:
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+ out = (mod_64(d, c->count) < ((c->count + 1) >> 1));
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+ break;
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+ case 4:
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+ case 5:
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+ out = (d == c->count);
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+ break;
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+ }
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+
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+ return out;
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+}
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+
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+static void pit_latch_count(struct kvm *kvm, int channel)
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+{
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+ struct kvm_kpit_channel_state *c =
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+ &kvm->arch.vpit->pit_state.channels[channel];
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+
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+ WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
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+
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+ if (!c->count_latched) {
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+ c->latched_count = pit_get_count(kvm, channel);
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+ c->count_latched = c->rw_mode;
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+ }
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+}
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+
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+static void pit_latch_status(struct kvm *kvm, int channel)
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+{
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+ struct kvm_kpit_channel_state *c =
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+ &kvm->arch.vpit->pit_state.channels[channel];
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+
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+ WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock));
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+
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+ if (!c->status_latched) {
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+ /* TODO: Return NULL COUNT (bit 6). */
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+ c->status = ((pit_get_out(kvm, channel) << 7) |
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+ (c->rw_mode << 4) |
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+ (c->mode << 1) |
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+ c->bcd);
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+ c->status_latched = 1;
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+ }
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+}
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+
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+int __pit_timer_fn(struct kvm_kpit_state *ps)
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+{
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+ struct kvm_vcpu *vcpu0 = ps->pit->kvm->vcpus[0];
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+ struct kvm_kpit_timer *pt = &ps->pit_timer;
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+
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+ atomic_inc(&pt->pending);
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+ smp_mb__after_atomic_inc();
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+ /* FIXME: handle case where the guest is in guest mode */
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+ if (vcpu0 && waitqueue_active(&vcpu0->wq)) {
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+ vcpu0->arch.mp_state = VCPU_MP_STATE_RUNNABLE;
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+ wake_up_interruptible(&vcpu0->wq);
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+ }
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+
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+ pt->timer.expires = ktime_add_ns(pt->timer.expires, pt->period);
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+ pt->scheduled = ktime_to_ns(pt->timer.expires);
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+
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+ return (pt->period == 0 ? 0 : 1);
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+}
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+
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+static enum hrtimer_restart pit_timer_fn(struct hrtimer *data)
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+{
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+ struct kvm_kpit_state *ps;
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+ int restart_timer = 0;
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+
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+ ps = container_of(data, struct kvm_kpit_state, pit_timer.timer);
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+
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+ restart_timer = __pit_timer_fn(ps);
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+
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+ if (restart_timer)
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+ return HRTIMER_RESTART;
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+ else
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+ return HRTIMER_NORESTART;
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+}
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+
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+static void destroy_pit_timer(struct kvm_kpit_timer *pt)
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+{
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+ pr_debug("pit: execute del timer!\n");
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+ hrtimer_cancel(&pt->timer);
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+}
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+
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+static void create_pit_timer(struct kvm_kpit_timer *pt, u32 val, int is_period)
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+{
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+ s64 interval;
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+
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+ interval = muldiv64(val, NSEC_PER_SEC, KVM_PIT_FREQ);
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+
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+ pr_debug("pit: create pit timer, interval is %llu nsec\n", interval);
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+
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+ /* TODO The new value only affected after the retriggered */
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+ hrtimer_cancel(&pt->timer);
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+ pt->period = (is_period == 0) ? 0 : interval;
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+ pt->timer.function = pit_timer_fn;
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+ atomic_set(&pt->pending, 0);
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+
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+ hrtimer_start(&pt->timer, ktime_add_ns(ktime_get(), interval),
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+ HRTIMER_MODE_ABS);
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+}
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+
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+static void pit_load_count(struct kvm *kvm, int channel, u32 val)
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+{
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+ struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state;
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+
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+ WARN_ON(!mutex_is_locked(&ps->lock));
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+
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+ pr_debug("pit: load_count val is %d, channel is %d\n", val, channel);
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+
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+ /*
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+ * Though spec said the state of 8254 is undefined after power-up,
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+ * seems some tricky OS like Windows XP depends on IRQ0 interrupt
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+ * when booting up.
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+ * So here setting initialize rate for it, and not a specific number
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+ */
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+ if (val == 0)
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+ val = 0x10000;
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+
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+ ps->channels[channel].count_load_time = ktime_get();
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+ ps->channels[channel].count = val;
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+
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+ if (channel != 0)
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+ return;
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+
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+ /* Two types of timer
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+ * mode 1 is one shot, mode 2 is period, otherwise del timer */
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+ switch (ps->channels[0].mode) {
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+ case 1:
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+ create_pit_timer(&ps->pit_timer, val, 0);
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+ break;
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+ case 2:
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+ create_pit_timer(&ps->pit_timer, val, 1);
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+ break;
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+ default:
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+ destroy_pit_timer(&ps->pit_timer);
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+ }
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+}
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+
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+static void pit_ioport_write(struct kvm_io_device *this,
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+ gpa_t addr, int len, const void *data)
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+{
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+ struct kvm_pit *pit = (struct kvm_pit *)this->private;
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+ struct kvm_kpit_state *pit_state = &pit->pit_state;
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+ struct kvm *kvm = pit->kvm;
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+ int channel, access;
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+ struct kvm_kpit_channel_state *s;
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+ u32 val = *(u32 *) data;
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+
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+ val &= 0xff;
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+ addr &= KVM_PIT_CHANNEL_MASK;
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+
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+ mutex_lock(&pit_state->lock);
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+
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+ if (val != 0)
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+ pr_debug("pit: write addr is 0x%x, len is %d, val is 0x%x\n",
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+ (unsigned int)addr, len, val);
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+
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+ if (addr == 3) {
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+ channel = val >> 6;
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+ if (channel == 3) {
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+ /* Read-Back Command. */
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+ for (channel = 0; channel < 3; channel++) {
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+ s = &pit_state->channels[channel];
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+ if (val & (2 << channel)) {
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+ if (!(val & 0x20))
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+ pit_latch_count(kvm, channel);
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+ if (!(val & 0x10))
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+ pit_latch_status(kvm, channel);
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+ }
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+ }
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+ } else {
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+ /* Select Counter <channel>. */
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+ s = &pit_state->channels[channel];
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+ access = (val >> 4) & KVM_PIT_CHANNEL_MASK;
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+ if (access == 0) {
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+ pit_latch_count(kvm, channel);
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+ } else {
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+ s->rw_mode = access;
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+ s->read_state = access;
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+ s->write_state = access;
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+ s->mode = (val >> 1) & 7;
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+ if (s->mode > 5)
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+ s->mode -= 4;
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+ s->bcd = val & 1;
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+ }
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+ }
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+ } else {
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+ /* Write Count. */
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+ s = &pit_state->channels[addr];
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+ switch (s->write_state) {
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+ default:
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+ case RW_STATE_LSB:
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+ pit_load_count(kvm, addr, val);
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+ break;
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+ case RW_STATE_MSB:
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+ pit_load_count(kvm, addr, val << 8);
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+ break;
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+ case RW_STATE_WORD0:
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+ s->write_latch = val;
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+ s->write_state = RW_STATE_WORD1;
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+ break;
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+ case RW_STATE_WORD1:
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+ pit_load_count(kvm, addr, s->write_latch | (val << 8));
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+ s->write_state = RW_STATE_WORD0;
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+ break;
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+ }
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+ }
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+
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+ mutex_unlock(&pit_state->lock);
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+}
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+
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+static void pit_ioport_read(struct kvm_io_device *this,
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+ gpa_t addr, int len, void *data)
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+{
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+ struct kvm_pit *pit = (struct kvm_pit *)this->private;
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+ struct kvm_kpit_state *pit_state = &pit->pit_state;
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+ struct kvm *kvm = pit->kvm;
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+ int ret, count;
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+ struct kvm_kpit_channel_state *s;
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+
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+ addr &= KVM_PIT_CHANNEL_MASK;
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+ s = &pit_state->channels[addr];
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+
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+ mutex_lock(&pit_state->lock);
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+
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+ if (s->status_latched) {
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+ s->status_latched = 0;
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+ ret = s->status;
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+ } else if (s->count_latched) {
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+ switch (s->count_latched) {
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+ default:
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+ case RW_STATE_LSB:
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+ ret = s->latched_count & 0xff;
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+ s->count_latched = 0;
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+ break;
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+ case RW_STATE_MSB:
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+ ret = s->latched_count >> 8;
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+ s->count_latched = 0;
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+ break;
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+ case RW_STATE_WORD0:
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+ ret = s->latched_count & 0xff;
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+ s->count_latched = RW_STATE_MSB;
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+ break;
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+ }
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+ } else {
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+ switch (s->read_state) {
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+ default:
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+ case RW_STATE_LSB:
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+ count = pit_get_count(kvm, addr);
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+ ret = count & 0xff;
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+ break;
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+ case RW_STATE_MSB:
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+ count = pit_get_count(kvm, addr);
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+ ret = (count >> 8) & 0xff;
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+ break;
|
|
|
+ case RW_STATE_WORD0:
|
|
|
+ count = pit_get_count(kvm, addr);
|
|
|
+ ret = count & 0xff;
|
|
|
+ s->read_state = RW_STATE_WORD1;
|
|
|
+ break;
|
|
|
+ case RW_STATE_WORD1:
|
|
|
+ count = pit_get_count(kvm, addr);
|
|
|
+ ret = (count >> 8) & 0xff;
|
|
|
+ s->read_state = RW_STATE_WORD0;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ if (len > sizeof(ret))
|
|
|
+ len = sizeof(ret);
|
|
|
+ memcpy(data, (char *)&ret, len);
|
|
|
+
|
|
|
+ mutex_unlock(&pit_state->lock);
|
|
|
+}
|
|
|
+
|
|
|
+static int pit_in_range(struct kvm_io_device *this, gpa_t addr)
|
|
|
+{
|
|
|
+ return ((addr >= KVM_PIT_BASE_ADDRESS) &&
|
|
|
+ (addr < KVM_PIT_BASE_ADDRESS + KVM_PIT_MEM_LENGTH));
|
|
|
+}
|
|
|
+
|
|
|
+static void speaker_ioport_write(struct kvm_io_device *this,
|
|
|
+ gpa_t addr, int len, const void *data)
|
|
|
+{
|
|
|
+ struct kvm_pit *pit = (struct kvm_pit *)this->private;
|
|
|
+ struct kvm_kpit_state *pit_state = &pit->pit_state;
|
|
|
+ struct kvm *kvm = pit->kvm;
|
|
|
+ u32 val = *(u32 *) data;
|
|
|
+
|
|
|
+ mutex_lock(&pit_state->lock);
|
|
|
+ pit_state->speaker_data_on = (val >> 1) & 1;
|
|
|
+ pit_set_gate(kvm, 2, val & 1);
|
|
|
+ mutex_unlock(&pit_state->lock);
|
|
|
+}
|
|
|
+
|
|
|
+static void speaker_ioport_read(struct kvm_io_device *this,
|
|
|
+ gpa_t addr, int len, void *data)
|
|
|
+{
|
|
|
+ struct kvm_pit *pit = (struct kvm_pit *)this->private;
|
|
|
+ struct kvm_kpit_state *pit_state = &pit->pit_state;
|
|
|
+ struct kvm *kvm = pit->kvm;
|
|
|
+ unsigned int refresh_clock;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ /* Refresh clock toggles at about 15us. We approximate as 2^14ns. */
|
|
|
+ refresh_clock = ((unsigned int)ktime_to_ns(ktime_get()) >> 14) & 1;
|
|
|
+
|
|
|
+ mutex_lock(&pit_state->lock);
|
|
|
+ ret = ((pit_state->speaker_data_on << 1) | pit_get_gate(kvm, 2) |
|
|
|
+ (pit_get_out(kvm, 2) << 5) | (refresh_clock << 4));
|
|
|
+ if (len > sizeof(ret))
|
|
|
+ len = sizeof(ret);
|
|
|
+ memcpy(data, (char *)&ret, len);
|
|
|
+ mutex_unlock(&pit_state->lock);
|
|
|
+}
|
|
|
+
|
|
|
+static int speaker_in_range(struct kvm_io_device *this, gpa_t addr)
|
|
|
+{
|
|
|
+ return (addr == KVM_SPEAKER_BASE_ADDRESS);
|
|
|
+}
|
|
|
+
|
|
|
+struct kvm_pit *kvm_create_pit(struct kvm *kvm)
|
|
|
+{
|
|
|
+ int i;
|
|
|
+ struct kvm_pit *pit;
|
|
|
+ struct kvm_kpit_state *pit_state;
|
|
|
+ struct kvm_kpit_channel_state *c;
|
|
|
+
|
|
|
+ pit = kzalloc(sizeof(struct kvm_pit), GFP_KERNEL);
|
|
|
+ if (!pit)
|
|
|
+ return NULL;
|
|
|
+
|
|
|
+ mutex_init(&pit->pit_state.lock);
|
|
|
+ mutex_lock(&pit->pit_state.lock);
|
|
|
+
|
|
|
+ /* Initialize PIO device */
|
|
|
+ pit->dev.read = pit_ioport_read;
|
|
|
+ pit->dev.write = pit_ioport_write;
|
|
|
+ pit->dev.in_range = pit_in_range;
|
|
|
+ pit->dev.private = pit;
|
|
|
+ kvm_io_bus_register_dev(&kvm->pio_bus, &pit->dev);
|
|
|
+
|
|
|
+ pit->speaker_dev.read = speaker_ioport_read;
|
|
|
+ pit->speaker_dev.write = speaker_ioport_write;
|
|
|
+ pit->speaker_dev.in_range = speaker_in_range;
|
|
|
+ pit->speaker_dev.private = pit;
|
|
|
+ kvm_io_bus_register_dev(&kvm->pio_bus, &pit->speaker_dev);
|
|
|
+
|
|
|
+ kvm->arch.vpit = pit;
|
|
|
+ pit->kvm = kvm;
|
|
|
+
|
|
|
+ pit_state = &pit->pit_state;
|
|
|
+ pit_state->pit = pit;
|
|
|
+ hrtimer_init(&pit_state->pit_timer.timer,
|
|
|
+ CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
|
|
|
+ atomic_set(&pit_state->pit_timer.pending, 0);
|
|
|
+ for (i = 0; i < 3; i++) {
|
|
|
+ c = &pit_state->channels[i];
|
|
|
+ c->mode = 0xff;
|
|
|
+ c->gate = (i != 2);
|
|
|
+ pit_load_count(kvm, i, 0);
|
|
|
+ }
|
|
|
+
|
|
|
+ mutex_unlock(&pit->pit_state.lock);
|
|
|
+
|
|
|
+ pit->pit_state.inject_pending = 1;
|
|
|
+
|
|
|
+ return pit;
|
|
|
+}
|
|
|
+
|
|
|
+void kvm_free_pit(struct kvm *kvm)
|
|
|
+{
|
|
|
+ struct hrtimer *timer;
|
|
|
+
|
|
|
+ if (kvm->arch.vpit) {
|
|
|
+ mutex_lock(&kvm->arch.vpit->pit_state.lock);
|
|
|
+ timer = &kvm->arch.vpit->pit_state.pit_timer.timer;
|
|
|
+ hrtimer_cancel(timer);
|
|
|
+ mutex_unlock(&kvm->arch.vpit->pit_state.lock);
|
|
|
+ kfree(kvm->arch.vpit);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+void __inject_pit_timer_intr(struct kvm *kvm)
|
|
|
+{
|
|
|
+ mutex_lock(&kvm->lock);
|
|
|
+ kvm_ioapic_set_irq(kvm->arch.vioapic, 0, 1);
|
|
|
+ kvm_ioapic_set_irq(kvm->arch.vioapic, 0, 0);
|
|
|
+ kvm_pic_set_irq(pic_irqchip(kvm), 0, 1);
|
|
|
+ kvm_pic_set_irq(pic_irqchip(kvm), 0, 0);
|
|
|
+ mutex_unlock(&kvm->lock);
|
|
|
+}
|
|
|
+
|
|
|
+void kvm_inject_pit_timer_irqs(struct kvm_vcpu *vcpu)
|
|
|
+{
|
|
|
+ struct kvm_pit *pit = vcpu->kvm->arch.vpit;
|
|
|
+ struct kvm *kvm = vcpu->kvm;
|
|
|
+ struct kvm_kpit_state *ps;
|
|
|
+
|
|
|
+ if (vcpu && pit) {
|
|
|
+ ps = &pit->pit_state;
|
|
|
+
|
|
|
+ /* Try to inject pending interrupts when:
|
|
|
+ * 1. Pending exists
|
|
|
+ * 2. Last interrupt was accepted or waited for too long time*/
|
|
|
+ if (atomic_read(&ps->pit_timer.pending) &&
|
|
|
+ (ps->inject_pending ||
|
|
|
+ (jiffies - ps->last_injected_time
|
|
|
+ >= KVM_MAX_PIT_INTR_INTERVAL))) {
|
|
|
+ ps->inject_pending = 0;
|
|
|
+ __inject_pit_timer_intr(kvm);
|
|
|
+ ps->last_injected_time = jiffies;
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+void kvm_pit_timer_intr_post(struct kvm_vcpu *vcpu, int vec)
|
|
|
+{
|
|
|
+ struct kvm_arch *arch = &vcpu->kvm->arch;
|
|
|
+ struct kvm_kpit_state *ps;
|
|
|
+
|
|
|
+ if (vcpu && arch->vpit) {
|
|
|
+ ps = &arch->vpit->pit_state;
|
|
|
+ if (atomic_read(&ps->pit_timer.pending) &&
|
|
|
+ (((arch->vpic->pics[0].imr & 1) == 0 &&
|
|
|
+ arch->vpic->pics[0].irq_base == vec) ||
|
|
|
+ (arch->vioapic->redirtbl[0].fields.vector == vec &&
|
|
|
+ arch->vioapic->redirtbl[0].fields.mask != 1))) {
|
|
|
+ ps->inject_pending = 1;
|
|
|
+ atomic_dec(&ps->pit_timer.pending);
|
|
|
+ ps->channels[0].count_load_time = ktime_get();
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|