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@@ -30,6 +30,29 @@ int __nongpreldata pcibios_last_bus = -1;
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struct pci_bus *__nongpreldata pci_root_bus;
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struct pci_ops *__nongpreldata pci_root_ops;
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+/*
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+ * The accessible PCI window does not cover the entire CPU address space, but
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+ * there are devices we want to access outside of that window, so we need to
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+ * insert specific PCI bus resources instead of using the platform-level bus
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+ * resources directly for the PCI root bus.
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+ *
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+ * These are configured and inserted by pcibios_init() and are attached to the
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+ * root bus by pcibios_fixup_bus().
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+ */
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+static struct resource pci_ioport_resource = {
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+ .name = "PCI IO",
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+ .start = 0,
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+ .end = IO_SPACE_LIMIT,
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+ .flags = IORESOURCE_IO,
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+};
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+
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+static struct resource pci_iomem_resource = {
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+ .name = "PCI mem",
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+ .start = 0,
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+ .end = -1,
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+ .flags = IORESOURCE_MEM,
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+};
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+
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/*
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* Functions for accessing PCI configuration space
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*/
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@@ -304,6 +327,12 @@ void __init pcibios_fixup_bus(struct pci_bus *bus)
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#if 0
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printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus->number);
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#endif
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+
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+ if (bus->number == 0) {
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+ bus->resource[0] = &pci_ioport_resource;
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+ bus->resource[1] = &pci_iomem_resource;
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+ }
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+
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pci_read_bridge_bases(bus);
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if (bus->number == 0) {
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@@ -350,28 +379,36 @@ int __init pcibios_init(void)
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/* enable PCI arbitration */
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__reg_MB86943_pci_arbiter = MB86943_PCIARB_EN;
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- ioport_resource.start = (__reg_MB86943_sl_pci_io_base << 9) & 0xfffffc00;
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- ioport_resource.end = (__reg_MB86943_sl_pci_io_range << 9) | 0x3ff;
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- ioport_resource.end += ioport_resource.start;
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+ pci_ioport_resource.start = (__reg_MB86943_sl_pci_io_base << 9) & 0xfffffc00;
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+ pci_ioport_resource.end = (__reg_MB86943_sl_pci_io_range << 9) | 0x3ff;
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+ pci_ioport_resource.end += pci_ioport_resource.start;
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printk("PCI IO window: %08llx-%08llx\n",
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- (unsigned long long) ioport_resource.start,
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- (unsigned long long) ioport_resource.end);
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+ (unsigned long long) pci_ioport_resource.start,
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+ (unsigned long long) pci_ioport_resource.end);
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- iomem_resource.start = (__reg_MB86943_sl_pci_mem_base << 9) & 0xfffffc00;
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+ pci_iomem_resource.start = (__reg_MB86943_sl_pci_mem_base << 9) & 0xfffffc00;
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+ pci_iomem_resource.end = (__reg_MB86943_sl_pci_mem_range << 9) | 0x3ff;
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+ pci_iomem_resource.end += pci_iomem_resource.start;
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- /* Reserve somewhere to write to flush posted writes. */
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- iomem_resource.start += 0x400;
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-
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- iomem_resource.end = (__reg_MB86943_sl_pci_mem_range << 9) | 0x3ff;
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- iomem_resource.end += iomem_resource.start;
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+ /* Reserve somewhere to write to flush posted writes. This is used by
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+ * __flush_PCI_writes() from asm/io.h to force the write FIFO in the
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+ * CPU-PCI bridge to flush as this doesn't happen automatically when a
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+ * read is performed on the MB93090 development kit motherboard.
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+ */
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+ pci_iomem_resource.start += 0x400;
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printk("PCI MEM window: %08llx-%08llx\n",
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- (unsigned long long) iomem_resource.start,
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- (unsigned long long) iomem_resource.end);
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+ (unsigned long long) pci_iomem_resource.start,
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+ (unsigned long long) pci_iomem_resource.end);
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printk("PCI DMA memory: %08lx-%08lx\n",
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dma_coherent_mem_start, dma_coherent_mem_end);
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+ if (insert_resource(&iomem_resource, &pci_iomem_resource) < 0)
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+ panic("Unable to insert PCI IOMEM resource\n");
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+ if (insert_resource(&ioport_resource, &pci_ioport_resource) < 0)
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+ panic("Unable to insert PCI IOPORT resource\n");
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+
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if (!pci_probe)
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return -ENXIO;
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