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@@ -831,8 +831,10 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
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{
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
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+ struct drm_encoder *encoder = &intel_encoder->base;
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struct drm_i915_private *dev_priv = crtc->dev->dev_private;
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enum pipe pipe = intel_crtc->pipe;
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+ int type = intel_encoder->type;
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uint32_t temp;
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/* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */
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@@ -861,9 +863,8 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
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if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
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temp |= PIPE_DDI_PHSYNC;
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- if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
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- struct intel_hdmi *intel_hdmi =
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- enc_to_intel_hdmi(&intel_encoder->base);
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+ if (type == INTEL_OUTPUT_HDMI) {
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+ struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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if (intel_hdmi->has_hdmi_sink)
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temp |= PIPE_DDI_MODE_SELECT_HDMI;
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@@ -871,9 +872,34 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
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temp |= PIPE_DDI_MODE_SELECT_DVI;
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temp |= PIPE_DDI_SELECT_PORT(intel_hdmi->ddi_port);
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- } else if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
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+
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+ } else if (type == INTEL_OUTPUT_ANALOG) {
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temp |= PIPE_DDI_MODE_SELECT_FDI;
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temp |= PIPE_DDI_SELECT_PORT(PORT_E);
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+
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+ } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
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+ type == INTEL_OUTPUT_EDP) {
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+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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+
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+ temp |= PIPE_DDI_MODE_SELECT_DP_SST;
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+ temp |= PIPE_DDI_SELECT_PORT(intel_dp->port);
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+
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+ switch (intel_dp->lane_count) {
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+ case 1:
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+ temp |= PIPE_DDI_PORT_WIDTH_X1;
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+ break;
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+ case 2:
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+ temp |= PIPE_DDI_PORT_WIDTH_X2;
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+ break;
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+ case 4:
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+ temp |= PIPE_DDI_PORT_WIDTH_X4;
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+ break;
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+ default:
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+ temp |= PIPE_DDI_PORT_WIDTH_X4;
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+ WARN(1, "Unsupported lane count %d\n",
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+ intel_dp->lane_count);
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+ }
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+
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} else {
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WARN(1, "Invalid encoder type %d for pipe %d\n",
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intel_encoder->type, pipe);
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