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@@ -30,6 +30,8 @@ enum sparc_cpu {
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#define ARCH_SUN4C_SUN4 0
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#define ARCH_SUN4 0
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+extern char reboot_command[];
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+
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/* These are here in an effort to more fully work around Spitfire Errata
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* #51. Essentially, if a memory barrier occurs soon after a mispredicted
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* branch, the chip can stop executing instructions until a trap occurs.
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