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@@ -765,6 +765,19 @@ static void ni_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
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ni_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
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}
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+bool ni_dpm_vblank_too_short(struct radeon_device *rdev)
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+{
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+ struct rv7xx_power_info *pi = rv770_get_pi(rdev);
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+ u32 vblank_time = r600_dpm_get_vblank_time(rdev);
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+ u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
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+
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+ if (vblank_time < switch_limit)
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+ return true;
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+ else
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+ return false;
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+
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+}
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+
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static void ni_apply_state_adjust_rules(struct radeon_device *rdev,
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struct radeon_ps *rps)
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{
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@@ -775,7 +788,8 @@ static void ni_apply_state_adjust_rules(struct radeon_device *rdev,
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u16 vddc, vddci;
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int i;
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- if (rdev->pm.dpm.new_active_crtc_count > 1)
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+ if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
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+ ni_dpm_vblank_too_short(rdev))
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disable_mclk_switching = true;
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else
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disable_mclk_switching = false;
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