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@@ -141,6 +141,7 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
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struct mlx4_cmd_mailbox *mailbox;
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u32 *outbox;
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u8 field;
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+ u32 field32;
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u16 size;
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u16 stat_rate;
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int err;
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@@ -368,6 +369,9 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
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#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
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#define QUERY_PORT_MAX_VL_OFFSET 0x0b
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#define QUERY_PORT_MAC_OFFSET 0x10
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+#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
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+#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
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+#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
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for (i = 1; i <= dev_cap->num_ports; ++i) {
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err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
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@@ -391,6 +395,11 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
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dev_cap->log_max_vlans[i] = field >> 4;
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MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
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MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
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+ MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
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+ dev_cap->trans_type[i] = field32 >> 24;
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+ dev_cap->vendor_oui[i] = field32 & 0xffffff;
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+ MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
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+ MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
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}
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}
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