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@@ -372,14 +372,28 @@ static int update_vport_qp_param(struct mlx4_dev *dev,
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if (MLX4_QP_ST_RC == qp_type)
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return -EINVAL;
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+ /* force strip vlan by clear vsd */
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+ qpc->param3 &= ~cpu_to_be32(MLX4_STRIP_VLAN);
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+ if (0 != vp_oper->state.default_vlan) {
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+ qpc->pri_path.vlan_control =
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+ MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
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+ MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
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+ MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
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+ } else { /* priority tagged */
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+ qpc->pri_path.vlan_control =
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+ MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
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+ MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
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+ }
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+
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+ qpc->pri_path.fvl_rx |= MLX4_FVL_RX_FORCE_ETH_VLAN;
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qpc->pri_path.vlan_index = vp_oper->vlan_idx;
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- qpc->pri_path.fl = (1 << 6) | (1 << 2); /* set cv bit and hide_cqe_vlan bit*/
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- qpc->pri_path.feup |= 1 << 3; /* set fvl bit */
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+ qpc->pri_path.fl |= MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
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+ qpc->pri_path.feup |= MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
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qpc->pri_path.sched_queue &= 0xC7;
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qpc->pri_path.sched_queue |= (vp_oper->state.default_qos) << 3;
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}
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if (vp_oper->state.spoofchk) {
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- qpc->pri_path.feup |= 1 << 5; /* set fsm bit */;
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+ qpc->pri_path.feup |= MLX4_FSM_FORCE_ETH_SRC_MAC;
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qpc->pri_path.grh_mylmc = (0x80 & qpc->pri_path.grh_mylmc) + vp_oper->mac_idx;
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}
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return 0;
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