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@@ -51,6 +51,20 @@
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#define IMX_CHIP_REVISION_3_3 0x33
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#define IMX_CHIP_REVISION_UNKNOWN 0xff
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+#define IMX_CHIP_REVISION_1_0_STRING "1.0"
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+#define IMX_CHIP_REVISION_1_1_STRING "1.1"
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+#define IMX_CHIP_REVISION_1_2_STRING "1.2"
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+#define IMX_CHIP_REVISION_1_3_STRING "1.3"
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+#define IMX_CHIP_REVISION_2_0_STRING "2.0"
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+#define IMX_CHIP_REVISION_2_1_STRING "2.1"
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+#define IMX_CHIP_REVISION_2_2_STRING "2.2"
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+#define IMX_CHIP_REVISION_2_3_STRING "2.3"
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+#define IMX_CHIP_REVISION_3_0_STRING "3.0"
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+#define IMX_CHIP_REVISION_3_1_STRING "3.1"
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+#define IMX_CHIP_REVISION_3_2_STRING "3.2"
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+#define IMX_CHIP_REVISION_3_3_STRING "3.3"
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+#define IMX_CHIP_REVISION_UNKNOWN_STRING "unknown"
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+
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#ifndef __ASSEMBLY__
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extern unsigned int __mxc_cpu_type;
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#endif
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