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@@ -24,13 +24,13 @@ struct snd_pcm_substream;
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* Describes the physical PCM data formating and clocking. Add new formats
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* to the end.
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*/
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-#define SND_SOC_DAIFMT_I2S 0 /* I2S mode */
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-#define SND_SOC_DAIFMT_RIGHT_J 1 /* Right Justified mode */
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-#define SND_SOC_DAIFMT_LEFT_J 2 /* Left Justified mode */
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-#define SND_SOC_DAIFMT_DSP_A 3 /* L data MSB after FRM LRC */
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-#define SND_SOC_DAIFMT_DSP_B 4 /* L data MSB during FRM LRC */
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-#define SND_SOC_DAIFMT_AC97 5 /* AC97 */
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-#define SND_SOC_DAIFMT_PDM 6 /* Pulse density modulation */
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+#define SND_SOC_DAIFMT_I2S 1 /* I2S mode */
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+#define SND_SOC_DAIFMT_RIGHT_J 2 /* Right Justified mode */
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+#define SND_SOC_DAIFMT_LEFT_J 3 /* Left Justified mode */
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+#define SND_SOC_DAIFMT_DSP_A 4 /* L data MSB after FRM LRC */
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+#define SND_SOC_DAIFMT_DSP_B 5 /* L data MSB during FRM LRC */
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+#define SND_SOC_DAIFMT_AC97 6 /* AC97 */
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+#define SND_SOC_DAIFMT_PDM 7 /* Pulse density modulation */
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/* left and right justified also known as MSB and LSB respectively */
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#define SND_SOC_DAIFMT_MSB SND_SOC_DAIFMT_LEFT_J
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@@ -42,8 +42,8 @@ struct snd_pcm_substream;
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* DAI bit clocks can be be gated (disabled) when the DAI is not
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* sending or receiving PCM data in a frame. This can be used to save power.
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*/
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-#define SND_SOC_DAIFMT_CONT (0 << 4) /* continuous clock */
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-#define SND_SOC_DAIFMT_GATED (1 << 4) /* clock is gated */
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+#define SND_SOC_DAIFMT_CONT (1 << 4) /* continuous clock */
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+#define SND_SOC_DAIFMT_GATED (2 << 4) /* clock is gated */
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/*
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* DAI hardware signal inversions.
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@@ -51,10 +51,10 @@ struct snd_pcm_substream;
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* Specifies whether the DAI can also support inverted clocks for the specified
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* format.
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*/
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-#define SND_SOC_DAIFMT_NB_NF (0 << 8) /* normal bit clock + frame */
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-#define SND_SOC_DAIFMT_NB_IF (1 << 8) /* normal BCLK + inv FRM */
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-#define SND_SOC_DAIFMT_IB_NF (2 << 8) /* invert BCLK + nor FRM */
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-#define SND_SOC_DAIFMT_IB_IF (3 << 8) /* invert BCLK + FRM */
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+#define SND_SOC_DAIFMT_NB_NF (1 << 8) /* normal bit clock + frame */
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+#define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */
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+#define SND_SOC_DAIFMT_IB_NF (3 << 8) /* invert BCLK + nor FRM */
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+#define SND_SOC_DAIFMT_IB_IF (4 << 8) /* invert BCLK + FRM */
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/*
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* DAI hardware clock masters.
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@@ -63,10 +63,10 @@ struct snd_pcm_substream;
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* i.e. if the codec is clk and FRM master then the interface is
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* clk and frame slave.
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*/
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-#define SND_SOC_DAIFMT_CBM_CFM (0 << 12) /* codec clk & FRM master */
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-#define SND_SOC_DAIFMT_CBS_CFM (1 << 12) /* codec clk slave & FRM master */
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-#define SND_SOC_DAIFMT_CBM_CFS (2 << 12) /* codec clk master & frame slave */
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-#define SND_SOC_DAIFMT_CBS_CFS (3 << 12) /* codec clk & FRM slave */
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+#define SND_SOC_DAIFMT_CBM_CFM (1 << 12) /* codec clk & FRM master */
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+#define SND_SOC_DAIFMT_CBS_CFM (2 << 12) /* codec clk slave & FRM master */
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+#define SND_SOC_DAIFMT_CBM_CFS (3 << 12) /* codec clk master & frame slave */
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+#define SND_SOC_DAIFMT_CBS_CFS (4 << 12) /* codec clk & FRM slave */
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#define SND_SOC_DAIFMT_FORMAT_MASK 0x000f
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#define SND_SOC_DAIFMT_CLOCK_MASK 0x00f0
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