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@@ -7,6 +7,9 @@
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*
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* Copyright (c) 1999 Martin Mares <mj@ucw.cz>
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*
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+ * Init/reset quirks for USB host controllers should be in the
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+ * USB quirks file, where their drivers can access reuse it.
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+ *
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* The bridge optimization stuff has been removed. If you really
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* have a silly BIOS which is unable to set your host bridge right,
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* use the PowerTweak utility (see http://powertweak.sourceforge.net).
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@@ -644,28 +647,6 @@ static void quirk_via_irq(struct pci_dev *dev)
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}
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DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_irq);
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-/*
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- * PIIX3 USB: We have to disable USB interrupts that are
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- * hardwired to PIRQD# and may be shared with an
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- * external device.
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- *
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- * Legacy Support Register (LEGSUP):
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- * bit13: USB PIRQ Enable (USBPIRQDEN),
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- * bit4: Trap/SMI On IRQ Enable (USBSMIEN).
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- *
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- * We mask out all r/wc bits, too.
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- */
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-static void __devinit quirk_piix3_usb(struct pci_dev *dev)
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-{
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- u16 legsup;
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-
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- pci_read_config_word(dev, 0xc0, &legsup);
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- legsup &= 0x50ef;
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- pci_write_config_word(dev, 0xc0, legsup);
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-}
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-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_2, quirk_piix3_usb );
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-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_2, quirk_piix3_usb );
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-
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/*
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* VIA VT82C598 has its device ID settable and many BIOSes
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* set it to the ID of VT82C597 for backward compatibility.
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@@ -1039,234 +1020,6 @@ static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
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pci_read_config_byte(dev, 0x77, &val);
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}
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-
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-#define UHCI_USBLEGSUP 0xc0 /* legacy support */
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-#define UHCI_USBCMD 0 /* command register */
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-#define UHCI_USBSTS 2 /* status register */
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-#define UHCI_USBINTR 4 /* interrupt register */
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-#define UHCI_USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
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-#define UHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
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-#define UHCI_USBCMD_GRESET (1 << 2) /* Global reset */
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-#define UHCI_USBCMD_CONFIGURE (1 << 6) /* config semaphore */
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-#define UHCI_USBSTS_HALTED (1 << 5) /* HCHalted bit */
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-
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-#define OHCI_CONTROL 0x04
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-#define OHCI_CMDSTATUS 0x08
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-#define OHCI_INTRSTATUS 0x0c
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-#define OHCI_INTRENABLE 0x10
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-#define OHCI_INTRDISABLE 0x14
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-#define OHCI_OCR (1 << 3) /* ownership change request */
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-#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
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-#define OHCI_INTR_OC (1 << 30) /* ownership change */
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-
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-#define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
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-#define EHCI_USBCMD 0 /* command register */
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-#define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
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-#define EHCI_USBSTS 4 /* status register */
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-#define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
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-#define EHCI_USBINTR 8 /* interrupt register */
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-#define EHCI_USBLEGSUP 0 /* legacy support register */
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-#define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
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-#define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
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-#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
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-#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
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-
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-int usb_early_handoff __devinitdata = 0;
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-static int __init usb_handoff_early(char *str)
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-{
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- usb_early_handoff = 1;
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- return 0;
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-}
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-__setup("usb-handoff", usb_handoff_early);
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-
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-static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
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-{
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- unsigned long base = 0;
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- int wait_time, delta;
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- u16 val, sts;
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- int i;
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-
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- for (i = 0; i < PCI_ROM_RESOURCE; i++)
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- if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
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- base = pci_resource_start(pdev, i);
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- break;
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- }
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-
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- if (!base)
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- return;
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-
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- /*
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- * stop controller
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- */
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- sts = inw(base + UHCI_USBSTS);
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- val = inw(base + UHCI_USBCMD);
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- val &= ~(u16)(UHCI_USBCMD_RUN | UHCI_USBCMD_CONFIGURE);
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- outw(val, base + UHCI_USBCMD);
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-
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- /*
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- * wait while it stops if it was running
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- */
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- if ((sts & UHCI_USBSTS_HALTED) == 0)
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- {
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- wait_time = 1000;
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- delta = 100;
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-
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- do {
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- outw(0x1f, base + UHCI_USBSTS);
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- udelay(delta);
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- wait_time -= delta;
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- val = inw(base + UHCI_USBSTS);
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- if (val & UHCI_USBSTS_HALTED)
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- break;
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- } while (wait_time > 0);
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- }
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-
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- /*
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- * disable interrupts & legacy support
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- */
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- outw(0, base + UHCI_USBINTR);
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- outw(0x1f, base + UHCI_USBSTS);
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- pci_read_config_word(pdev, UHCI_USBLEGSUP, &val);
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- if (val & 0xbf)
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- pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_DEFAULT);
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-
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-}
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-
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-static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
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-{
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- void __iomem *base;
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- int wait_time;
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-
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- base = ioremap_nocache(pci_resource_start(pdev, 0),
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- pci_resource_len(pdev, 0));
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- if (base == NULL) return;
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-
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- if (readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
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- wait_time = 500; /* 0.5 seconds */
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- writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
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- writel(OHCI_OCR, base + OHCI_CMDSTATUS);
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- while (wait_time > 0 &&
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- readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
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- wait_time -= 10;
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- msleep(10);
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- }
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- }
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-
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- /*
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- * disable interrupts
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- */
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- writel(~(u32)0, base + OHCI_INTRDISABLE);
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- writel(~(u32)0, base + OHCI_INTRSTATUS);
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-
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- iounmap(base);
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-}
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-
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-static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
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-{
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- int wait_time, delta;
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- void __iomem *base, *op_reg_base;
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- u32 hcc_params, val, temp;
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- u8 cap_length;
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-
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- base = ioremap_nocache(pci_resource_start(pdev, 0),
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- pci_resource_len(pdev, 0));
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- if (base == NULL) return;
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-
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- cap_length = readb(base);
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- op_reg_base = base + cap_length;
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- hcc_params = readl(base + EHCI_HCC_PARAMS);
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- hcc_params = (hcc_params >> 8) & 0xff;
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- if (hcc_params) {
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- pci_read_config_dword(pdev,
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- hcc_params + EHCI_USBLEGSUP,
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- &val);
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- if (((val & 0xff) == 1) && (val & EHCI_USBLEGSUP_BIOS)) {
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- /*
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- * Ok, BIOS is in smm mode, try to hand off...
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- */
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- pci_read_config_dword(pdev,
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- hcc_params + EHCI_USBLEGCTLSTS,
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- &temp);
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- pci_write_config_dword(pdev,
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- hcc_params + EHCI_USBLEGCTLSTS,
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- temp | EHCI_USBLEGCTLSTS_SOOE);
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- val |= EHCI_USBLEGSUP_OS;
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- pci_write_config_dword(pdev,
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- hcc_params + EHCI_USBLEGSUP,
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- val);
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-
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- wait_time = 500;
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- do {
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- msleep(10);
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- wait_time -= 10;
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- pci_read_config_dword(pdev,
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- hcc_params + EHCI_USBLEGSUP,
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- &val);
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- } while (wait_time && (val & EHCI_USBLEGSUP_BIOS));
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- if (!wait_time) {
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- /*
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- * well, possibly buggy BIOS...
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- */
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- printk(KERN_WARNING "EHCI early BIOS handoff "
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- "failed (BIOS bug ?)\n");
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- pci_write_config_dword(pdev,
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- hcc_params + EHCI_USBLEGSUP,
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- EHCI_USBLEGSUP_OS);
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- pci_write_config_dword(pdev,
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- hcc_params + EHCI_USBLEGCTLSTS,
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- 0);
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- }
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- }
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- }
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-
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- /*
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- * halt EHCI & disable its interrupts in any case
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- */
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- val = readl(op_reg_base + EHCI_USBSTS);
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- if ((val & EHCI_USBSTS_HALTED) == 0) {
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- val = readl(op_reg_base + EHCI_USBCMD);
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- val &= ~EHCI_USBCMD_RUN;
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- writel(val, op_reg_base + EHCI_USBCMD);
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-
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- wait_time = 2000;
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- delta = 100;
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- do {
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- writel(0x3f, op_reg_base + EHCI_USBSTS);
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- udelay(delta);
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- wait_time -= delta;
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- val = readl(op_reg_base + EHCI_USBSTS);
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- if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
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- break;
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- }
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- } while (wait_time > 0);
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- }
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- writel(0, op_reg_base + EHCI_USBINTR);
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- writel(0x3f, op_reg_base + EHCI_USBSTS);
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-
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- iounmap(base);
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-
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- return;
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-}
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-
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-
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-
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-static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
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-{
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- if (!usb_early_handoff)
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- return;
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-
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- if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x00)) { /* UHCI */
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- quirk_usb_handoff_uhci(pdev);
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- } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) { /* OHCI */
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- quirk_usb_handoff_ohci(pdev);
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- } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x20)) { /* EHCI */
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- quirk_usb_disable_ehci(pdev);
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- }
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-
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- return;
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-}
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-DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);
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-
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/*
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* ... This is further complicated by the fact that some SiS96x south
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* bridges pretend to be 85C503/5513 instead. In that case see if we
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