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@@ -1243,13 +1243,12 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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else
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ctrl &= ~SDHCI_CTRL_HISPD;
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- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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-
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if (host->version >= SDHCI_SPEC_300) {
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u16 ctrl_2;
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ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
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+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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/*
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* We only need to set Driver Strength if the
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* preset value enable is not set.
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@@ -1261,8 +1260,30 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
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sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
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+ } else {
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+ /*
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+ * According to SDHC Spec v3.00, if the Preset Value
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+ * Enable in the Host Control 2 register is set, we
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+ * need to reset SD Clock Enable before changing High
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+ * Speed Enable to avoid generating clock gliches.
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+ */
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+ u16 clk;
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+ unsigned int clock;
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+
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+ /* Reset SD Clock Enable */
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+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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+ clk &= ~SDHCI_CLOCK_CARD_EN;
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+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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+
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+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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+
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+ /* Re-enable SD Clock */
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+ clock = host->clock;
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+ host->clock = 0;
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+ sdhci_set_clock(host, clock);
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}
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- }
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+ } else
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+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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/*
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* Some (ENE) controllers go apeshit on some ios operation,
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