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@@ -1,78 +1,41 @@
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/*
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- * Low-Level PCI Support for the SH7751
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+ * Low-Level PCI Support for the SH7751
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*
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- * Dustin McIntire (dustin@sensoria.com)
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- * Derived from arch/i386/kernel/pci-*.c which bore the message:
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- * (c) 1999--2000 Martin Mares <mj@ucw.cz>
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+ * Copyright (C) 2003 - 2009 Paul Mundt
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+ * Copyright (C) 2001 Dustin McIntire
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*
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- * Ported to the new API by Paul Mundt <lethal@linux-sh.org>
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- * With cleanup by Paul van Gool <pvangool@mimotech.com>
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- *
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- * May be copied or modified under the terms of the GNU General Public
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- * License. See linux/COPYING for more information.
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+ * With cleanup by Paul van Gool <pvangool@mimotech.com>, 2003.
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*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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*/
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-#undef DEBUG
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-
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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-#include <linux/delay.h>
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+#include <linux/io.h>
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#include "pci-sh4.h"
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#include <asm/addrspace.h>
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-#include <asm/io.h>
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-
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-/*
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- * Initialization. Try all known PCI access methods. Note that we support
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- * using both PCI BIOS and direct access: in such cases, we use I/O ports
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- * to access config space.
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- *
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- * Note that the platform specific initialization (BSC registers, and memory
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- * space mapping) will be called via the platform defined function
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- * pcibios_init_platform().
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- */
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-int __init sh7751_pci_init(struct pci_channel *chan)
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-{
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- unsigned int id;
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- int ret;
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-
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- pr_debug("PCI: Starting intialization.\n");
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-
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- chan->reg_base = 0xfe200000;
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-
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- /* check for SH7751/SH7751R hardware */
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- id = pci_read_reg(chan, SH7751_PCICONF0);
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- if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
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- id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
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- pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
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- return -ENODEV;
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- }
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-
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- if ((ret = sh4_pci_check_direct(chan)) != 0)
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- return ret;
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-
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- return pcibios_init_platform();
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-}
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static int __init __area_sdram_check(struct pci_channel *chan,
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unsigned int area)
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{
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- u32 word;
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+ unsigned long word;
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- word = ctrl_inl(SH7751_BCR1);
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+ word = __raw_readl(SH7751_BCR1);
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/* check BCR for SDRAM in area */
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if (((word >> area) & 1) == 0) {
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- printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n",
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+ printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n",
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area, word);
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return 0;
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}
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pci_write_reg(chan, word, SH4_PCIBCR1);
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- word = (u16)ctrl_inw(SH7751_BCR2);
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+ word = __raw_readw(SH7751_BCR2);
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/* check BCR2 for 32bit SDRAM interface*/
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if (((word >> (area << 1)) & 0x3) != 0x3) {
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- printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n",
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+ printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n",
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area, word);
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return 0;
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}
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@@ -81,11 +44,56 @@ static int __init __area_sdram_check(struct pci_channel *chan,
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return 1;
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}
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-int __init sh7751_pcic_init(struct pci_channel *chan,
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- struct sh4_pci_address_map *map)
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+static struct resource sh7751_io_resource = {
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+ .name = "SH7751_IO",
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+ .start = SH7751_PCI_IO_BASE,
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+ .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
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+ .flags = IORESOURCE_IO
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+};
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+
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+static struct resource sh7751_mem_resource = {
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+ .name = "SH7785_mem",
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+ .start = SH7751_PCI_MEMORY_BASE,
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+ .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
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+ .flags = IORESOURCE_MEM
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+};
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+
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+static struct pci_channel sh7751_pci_controller = {
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+ .pci_ops = &sh4_pci_ops,
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+ .mem_resource = &sh7751_mem_resource,
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+ .mem_offset = 0x00000000,
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+ .io_resource = &sh7751_io_resource,
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+ .io_offset = 0x00000000,
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+};
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+
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+static struct sh4_pci_address_map sh7751_pci_map = {
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+ .window0 = {
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+ .base = SH7751_CS3_BASE_ADDR,
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+ .size = 0x04000000,
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+ },
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+};
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+
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+static int __init sh7751_pci_init(void)
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{
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- u32 reg;
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- u32 word;
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+ struct pci_channel *chan = &sh7751_pci_controller;
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+ unsigned int id;
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+ u32 word, reg;
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+ int ret;
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+
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+ printk(KERN_NOTICE "PCI: Starting intialization.\n");
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+
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+ chan->reg_base = 0xfe200000;
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+
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+ /* check for SH7751/SH7751R hardware */
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+ id = pci_read_reg(chan, SH7751_PCICONF0);
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+ if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
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+ id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
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+ pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
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+ return -ENODEV;
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+ }
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+
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+ if ((ret = sh4_pci_check_direct(chan)) != 0)
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+ return ret;
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/* Set the BCR's to enable PCI access */
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reg = ctrl_inl(SH7751_BCR1);
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@@ -112,21 +120,13 @@ int __init sh7751_pcic_init(struct pci_channel *chan,
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/* Set IO and Mem windows to local address
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* Make PCI and local address the same for easy 1 to 1 mapping
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- * Window0 = map->window0.size @ non-cached area base = SDRAM
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- * Window1 = map->window1.size @ cached area base = SDRAM
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*/
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- word = map->window0.size - 1;
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+ word = sh7751_pci_map.window0.size - 1;
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pci_write_reg(chan, word, SH4_PCILSR0);
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- word = map->window1.size - 1;
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- pci_write_reg(chan, word, SH4_PCILSR1);
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/* Set the values on window 0 PCI config registers */
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- word = P2SEGADDR(map->window0.base);
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+ word = P2SEGADDR(sh7751_pci_map.window0.base);
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pci_write_reg(chan, word, SH4_PCILAR0);
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pci_write_reg(chan, word, SH7751_PCICONF5);
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- /* Set the values on window 1 PCI config registers */
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- word = PHYSADDR(map->window1.base);
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- pci_write_reg(chan, word, SH4_PCILAR1);
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- pci_write_reg(chan, word, SH7751_PCICONF6);
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/* Set the local 16MB PCI memory space window to
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* the lowest PCI mapped address
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@@ -144,7 +144,7 @@ int __init sh7751_pcic_init(struct pci_channel *chan,
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/* Set PCI WCRx, BCRx's, copy from BSC locations */
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/* check BCR for SDRAM in specified area */
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- switch (map->window0.base) {
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+ switch (sh7751_pci_map.window0.base) {
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case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(chan, 0); break;
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case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(chan, 1); break;
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case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(chan, 2); break;
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@@ -179,5 +179,10 @@ int __init sh7751_pcic_init(struct pci_channel *chan,
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word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
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pci_write_reg(chan, word, SH4_PCICR);
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+ __set_io_port_base(SH7751_PCI_IO_BASE);
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+
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+ register_pci_controller(chan);
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+
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return 0;
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}
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+arch_initcall(sh7751_pci_init);
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Paul Mundt