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@@ -3705,6 +3705,15 @@ static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
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b43_write16(dev, B43_MMIO_PHY_DATA, value);
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}
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+static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
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+ u16 set)
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+{
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+ check_phyreg(dev, reg);
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+ b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
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+ b43_write16(dev, B43_MMIO_PHY_DATA,
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+ (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
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+}
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+
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static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
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{
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/* Register 1 is a 32-bit register. */
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@@ -3799,6 +3808,7 @@ const struct b43_phy_operations b43_phyops_n = {
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.init = b43_nphy_op_init,
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.phy_read = b43_nphy_op_read,
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.phy_write = b43_nphy_op_write,
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+ .phy_maskset = b43_nphy_op_maskset,
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.radio_read = b43_nphy_op_radio_read,
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.radio_write = b43_nphy_op_radio_write,
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.software_rfkill = b43_nphy_op_software_rfkill,
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