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@@ -101,9 +101,6 @@ do {if (net_ratelimit()) EFX_LOG(efx, fmt, ##args); } while (0)
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* Special buffers are used for the event queues and the TX and RX
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* descriptor queues for each channel. They are *not* used for the
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* actual transmit and receive buffers.
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- *
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- * Note that for Falcon, TX and RX descriptor queues live in host memory.
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- * Allocation and freeing procedures must take this into account.
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*/
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struct efx_special_buffer {
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void *addr;
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@@ -300,7 +297,7 @@ struct efx_rx_queue {
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* @dma_addr: DMA base address of the buffer
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* @len: Buffer length, in bytes
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*
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- * Falcon uses these buffers for its interrupt status registers and
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+ * The NIC uses these buffers for its interrupt status registers and
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* MAC stats dumps.
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*/
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struct efx_buffer {
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@@ -674,7 +671,7 @@ union efx_multicast_hash {
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* @irq_status: Interrupt status buffer
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* @last_irq_cpu: Last CPU to handle interrupt.
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* This register is written with the SMP processor ID whenever an
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- * interrupt is handled. It is used by falcon_test_interrupt()
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+ * interrupt is handled. It is used by efx_nic_test_interrupt()
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* to verify that an interrupt has occurred.
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* @spi_flash: SPI flash device
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* This field will be %NULL if no flash device is present (or for Siena).
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@@ -723,8 +720,7 @@ union efx_multicast_hash {
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* @loopback_modes: Supported loopback mode bitmask
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* @loopback_selftest: Offline self-test private state
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*
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- * The @priv field of the corresponding &struct net_device points to
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- * this.
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+ * This is stored in the private area of the &struct net_device.
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*/
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struct efx_nic {
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char name[IFNAMSIZ];
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@@ -997,7 +993,7 @@ static inline void clear_bit_le(unsigned nr, unsigned char *addr)
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* that the net driver will program into the MAC as the maximum frame
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* length.
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*
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- * The 10G MAC used in Falcon requires 8-byte alignment on the frame
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+ * The 10G MAC requires 8-byte alignment on the frame
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* length, so we round up to the nearest 8.
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*
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* Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
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