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@@ -9454,13 +9454,10 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
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an_1000_val);
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/* set 100 speed advertisement */
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- if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
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+ if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
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(phy->speed_cap_mask &
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(PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
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- PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) &&
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- (phy->supported &
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- (SUPPORTED_100baseT_Half |
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- SUPPORTED_100baseT_Full)))) {
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+ PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {
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an_10_100_val |= (1<<7);
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/* Enable autoneg and restart autoneg for legacy speeds */
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autoneg_val |= (1<<9 | 1<<12);
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@@ -11528,6 +11525,19 @@ static int bnx2x_populate_ext_phy(struct bnx2x *bp,
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}
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phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
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+ if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
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+ (phy->ver_addr)) {
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+ /*
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+ * Remove 100Mb link supported for BCM84833 when phy fw
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+ * version lower than or equal to 1.39
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+ */
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+ u32 raw_ver = REG_RD(bp, phy->ver_addr);
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+ if (((raw_ver & 0x7F) <= 39) &&
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+ (((raw_ver & 0xF80) >> 7) <= 1))
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+ phy->supported &= ~(SUPPORTED_100baseT_Half |
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+ SUPPORTED_100baseT_Full);
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+ }
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+
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/*
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* In case mdc/mdio_access of the external phy is different than the
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* mdc/mdio access of the XGXS, a HW lock must be taken in each access
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